1-4 Revision 13 Flash*Freeze Technology The IGLOOe device has an ultra-low power static mode, called Flash*Fr" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� M1AGLE3000V2-FGG896
寤犲晢锛� Microsemi SoC
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 2/166闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA 1KB FLASH 3M 896-FBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 27
绯诲垪锛� IGLOOe
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 75264
RAM 浣嶇附瑷�(j矛)锛� 516096
杓稿叆/杓稿嚭鏁�(sh霉)锛� 620
闁€(m茅n)鏁�(sh霉)锛� 3000000
闆绘簮闆诲锛� 1.14 V ~ 1.575 V
瀹夎椤�(l猫i)鍨嬶細 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 896-BGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 896-FBGA锛�31x31锛�
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IGLOOe Device Family Overview
1-4
Revision 13
Flash*Freeze Technology
The IGLOOe device has an ultra-low power static mode, called Flash*Freeze mode, which retains all
SRAM and register information and can still quickly return to normal operation. Flash*Freeze technology
enables the user to quickly (within 1 s) enter and exit Flash*Freeze mode by activating the
Flash*Freeze pin while all power supplies are kept at their original values. In addition, I/Os and global
I/Os can still be driven and can be toggling without impact on power consumption, clocks can still be
driven or can be toggling without impact on power consumption, and the device retains all core registers,
SRAM information, and states. I/O states are tristated during Flash*Freeze mode or can be set to a
certain state using weak pull-up or pull-down I/O attribute configuration. No power is consumed by the
I/O banks, clocks, JTAG pins, or PLL in this mode.
Flash*Freeze technology allows the user to switch to active mode on demand, thus simplifying the power
management of the device.
The Flash*Freeze pin (active low) can be routed internally to the core to allow the user's logic to decide
when it is safe to transition to this mode. It is also possible to use the Flash*Freeze pin as a regular I/O if
Flash*Freeze mode usage is not planned, which is advantageous because of the inherent low power
static and dynamic capabilities of the IGLOOe device. Refer to Figure 1-2 for an illustration of
entering/exiting Flash*Freeze mode.
Figure 1-1 IGLOOe Device Architecture Overview
Figure 1-2 IGLOOe Flash*Freeze Mode
4,608-Bit Dual-Port SRAM
or FIFO Block
VersaTile
RAM Block
CCC
Pro I/Os
4,608-Bit Dual-Port SRAM
or FIFO Block
RAM Block
ISP AES
Decryption*
User Nonvolatile
FlashRom
Flash*Freeze
Technology
Charge
Pumps
IGLOOe
FPGA
Flash*Freeze
Mode Control
Flash*Freeze Pin
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
M1AGLE3000V2-FG896 IC FPGA 1KB FLASH 3M 896-FBGA
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鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
M1AGLE3000V2-FGG896ES 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū(ch膿ng):Actel Corporation 鍔熻兘鎻忚堪:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
M1AGLE3000V2-FGG896I 鍔熻兘鎻忚堪:IC FPGA 1KB FLASH 3M 896-FBGA RoHS:鏄� 椤�(l猫i)鍒�:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄e垪锛� 绯诲垪:IGLOOe 妯�(bi膩o)婧�(zh菙n)鍖呰:1 绯诲垪:ProASICPLUS LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):129024 杓稿叆/杓稿嚭鏁�(sh霉):248 闁€(m茅n)鏁�(sh霉):600000 闆绘簮闆诲:2.3 V ~ 2.7 V 瀹夎椤�(l猫i)鍨�:琛ㄩ潰璨艰 宸ヤ綔婧害:- 灏佽/澶栨:352-BFCQFP锛屽付鎷夋】 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:352-CQFP锛�75x75锛�
M1AGLE3000V2-FGG896PP 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū(ch膿ng):Actel Corporation 鍔熻兘鎻忚堪:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
M1AGLE3000V5-FFG484 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:FPGA IGLOOE 3M GATES 130NM 1.5V 484FBGA - Trays
M1AGLE3000V5-FFG896 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:FPGA IGLOOE 3M GATES 130NM 1.5V 896FBGA - Trays