5-8 Revision 13 Advance v0.5 (continued) The "RESET" section was updated. 2-25 The "RESET" section was u" />
參數(shù)資料
型號： M1A3PE3000-PQG208I
廠商： Microsemi SoC
文件頁數(shù)： 66/162頁
文件大?。?/td> 0K
描述： IC FPGA 1KB FLASH 3M 208-PQFP
標(biāo)準(zhǔn)包裝： 24
系列： ProASIC3E
RAM 位總計： 516096
輸入/輸出數(shù)： 147
門數(shù)： 3000000
電源電壓： 1.425 V ~ 1.575 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 208-BFQFP
供應(yīng)商設(shè)備封裝： 208-PQFP（28x28）
Datasheet Information
5-8
Revision 13
Advance v0.5
(continued)
The "RESET" section was updated.
2-25
The "RESET" section was updated.
2-27
The "Introduction" of the "Introduction" section was updated.
2-28
PCI-X 3.3 V was added to the Compatible Standards for 3.3 V in Table 2-
11 VCCI Voltages and Compatible Standards
2-29
Table 2-35 ProASIC3E I/O Features was updated.
2-54
The "Double Data Rate (DDR) Support" section was updated to include
information concerning implementation of the feature.
2-32
The "Electrostatic Discharge (ESD) Protection" section was updated to include
testing information.
2-35
Level 3 and 4 descriptions were updated in Table 2-43 I/O Hot-Swap and 5 V
Input Tolerance Capabilities in ProASIC3 Devices.
2-64
The notes in Table 2-45 I/O Hot-Swap and 5 V Input Tolerance Capabilities in
ProASIC3E Devices were updated.
2-64
The "Simultaneous Switching Outputs (SSOs) and Printed Circuit Board Layout"
section is new.
2-41
A footnote was added to Table 2-37 Maximum I/O Frequency for Single-Ended
and Differential I/Os in All Banks in ProASIC3E Devices (maximum drive strength
and high slew selected).
2-55
Table 2-48 ProASIC3E I/O Attributes vs. I/O Standard Applications
2-81
Table 2-55 ProASIC3 I/O Standards—SLEW and Output Drive (OUT_DRIVE)
Settings
2-85
The "x" was updated in the "Pin Descriptions" section.
2-50
The "VCC Core Supply Voltage" pin description was updated.
2-50
The "VMVx I/O Supply Voltage (quiet)" pin description was updated to include
information concerning leaving the pin unconnected.
2-50
EXTFB was removed from Figure 2-24 ProASIC3E CCC Options.
2-24
The CCC Output Peak-to-Peak Period Jitter FCCC_OUT was updated in Table
2-13 ProASIC3E CCC/PLL Specification.
2-30
EXTFB was removed from Figure 2-27 CCC/PLL Macro.
2-28
The LVPECL specification in Table 2-45 I/O Hot-Swap and 5 V Input Tolerance
Capabilities in ProASIC3E Devices was updated.
2-64
Table 2-15 Levels of Hot-Swap Support was updated.
2-34
The "Cold-Sparing Support" section was updated.
2-34
"Electrostatic Discharge (ESD) Protection" section was updated.
2-35
The VJTAG and I/O pin descriptions were updated in the "Pin Descriptions"
section.
2-50
The "VJTAG JTAG Supply Voltage" pin description was updated.
2-50
The "VPUMP Programming Supply Voltage" pin description was updated to
include information on what happens when the pin is tied to ground.
2-50
Revision
Changes
Page
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