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| 型號(hào)： | M1026-1Z-173.3708 |
| 英文描述： | VCSO BASED CLOCK PLL WITH AUTOSWITCH |
| 中文描述： | 才能開(kāi)發(fā)出復(fù)雜基于時(shí)鐘鎖相環(huán)AUTOSWITCH |
| 文件頁(yè)數(shù)： | 12/14頁(yè) |
| 文件大小： | 322K |
| 代理商： | M1026-1Z-173.3708 |
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M1025/26 Datasheet Rev 1.0
12
of 14
Revised 28Jul2004
Integrated Circuit Systems, Inc.
●
Networking & Communications
●
www.icst.com
●
tel (508) 852-5400
Integrated
Circuit
Systems, Inc.
M1025/26
VCSO B
ASED
C
LOCK
PLL
WITH
A
UTO
S
WITCH
P r o d u c t D a t a S h e e t
E
LECTRICAL
S
PECIFICATIONS
(
CONTINUED
)
P
ARAMETER
M
EASUREMENT
I
NFORMATION
Output Rise and Fall Time
Figure 6: Output Rise and Fall Time
Output Duty Cycle
Figure 7: Output Duty Cycle
AC Characteristics
Unless stated otherwise, V
=
3.3
V +
5
%,T
A
=
0
o
C
to +
70
o
C (commercial), T
A
=
-40
o
C
to +
85
o
C (industrial), F
VCSO
= F
OUT
=
150-
175MHz,
LVPECL outputs termnated with
50
to V
CC
- 2V
Symbol Parameter
F
IN
Input Frequency
DIF_REF0, nDIF_REF0,
DIF_REF1, nDIF_REF1
Min
Typ
Max
Unit Conditions
15
700
MHz
F
OUT
Output Frequency
FOUT nFOUT
62.5
175
MHz
APR
Absolute Pull-Range
of VCSO
Commercial
Industrial
±
120
±
50
±
200
±
150
200
ppm
ppm
kHz/V
k
k
kHz
PLL Loop
Constants
1
Note 1: Parameters needed for PLL Simulator software; see Table 7, Example External Loop Filter Component Values, on pg. 9.
Note 2: See Parameter Measurement Information on pg. 12.
K
VCO
R
IN
VCO Gain
Internal Loop Resistor
Wde Bandwidth
100
Narrow Bandwidth
2100
BW
VCSO
VCSO Bandwidth
Φ
n
Single Side Band
Phase Noise
@
155.52
MHz
700
Phase Noise
and Jitter
1
kHz Offset
10
kHz Offset
100
kHz Offset
-
83
-
113
-
136
dBc/Hz
Fin=19.44 or
38.88_MHz
Tot.PLL ratio = 8
or 4. See
pg. 3
dBc/Hz
dBc/Hz
J(t)
Jitter (rms)
@
155.52
MHz
Output Duty Cycle
2
Output Rise Time
2
for
FOUT
nFOUT
Output Fall Time
2
for
FOUT
nFOUT
12
kHz to
20
MHz
0.4
0.6
ps
odc
45
50
55
%
t
R
350
450
550
ps
20
%
to
80
%
t
F
350
450
550
ps
20
%
to
80
%
Table 11: AC Characteristics
20%
80%
t
R
20%
t
F
80%
Clock Output
V
P
-
P
nFOUT
FOUT
t
t
PERIOD
(Output Pulse Width)
t
PERIOD
t
PW
odc =
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