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參數(shù)資料
| 型號： | LZ93N61 |
| 廠商： | Sharp Corporation |
| 英文描述： | Timing Pulse Generator LSI for CCD |
| 中文描述： | 時序脈沖發(fā)生器LSI的防治荒漠化公約 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 267K |
| 代理商： | LZ93N61 |
I
PIN NAME
--------
15
SPI
and SP2 phase
control input 1
The
pulses
pin sets the falling edge of
(pin 13) and SP2 (pin 14).
sampling
16
SP12
and
phase
The SP12 pin sets the rising edge of color sampling
pulses SPI (pin 13) and SP2 (pin 14).
control input 2
17
FS
o
CDS pulse 2
The FS pin outputs the pulses for sampling output
signals of
18
1
FS phase control input 1
The
pin sets the phase of the FS (pin 17).
19
FS phase control input
The
pin sets the width of the FS (pin 17).
20
FCDS
o
FCDS pulse 1
The FCDS pin outputs the pulse to clamp the out-
put signals of
21
c11
FCDS phase control
input 1
The Cl pin sets the phase of the FCDS (pin 20).
22
C12
FCDS phase control
input 2
The
pin sets the width of the FCDS (pin 20).
23
RI
FR phase control
input 1
The RI
I
pin sets the pahse of the FR (pin 42).
24
FR phase control
input 2
The
pin sets the width of the FR (pin 42).
25
MCKI
o
Clock output 1
The MCKI pin outputs 1/2 dividing pulse of
46). It is the same phase with the FH (pin 45).
(pin
The MCK2 pin outputs 1/2
46). It is delayad by approximately
respect to FH1 (pin 45).
pulse of
in phase with
(pin
26
MCK2
o
Clink output 2
27
MCK3
o
output 3
MCK3 pin outputs 1/2 dividing pulse of
46). It is the same phase with the
(pin
(pin 44).
The
46). It is delayed by approximately
respect to FH2 (pin 44).
pin outputs 1/2 dividing pulse of
(pin
28
MCK4
o
Clock output 4
in phase
The SE pin outputs the demodulation carrier of out-
put signals of CCD, and input the switching signal
of color sampling pulses
14). It outputs 1/4 dividing pulse of the
(pin 46), and selects the phase in
the SESL (pin 32) and the SINV (pin 34).
29
SE
o
Color demodulation
(pin 13) and
(pin
input
with
–
—
Power supply
The Vcc is a + 5 V power supply pin.
31
GND
–
–
Ground
The GND is a ground pin.
291
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