參數(shù)資料
型號(hào): LZ93N19
廠商: Sharp Corporation
英文描述: CAP 0.082UF 50V 50V X7R RAD.20 .20X.20 BULK R-MIL-PRF-39014 STANDOFF
中文描述: 同步信號(hào)發(fā)生器的防治荒漠化公約
文件頁數(shù): 5/11頁
文件大?。?/td> 234K
代理商: LZ93N19
SYMBOL
PIN NAME
FUNCTION
An input pin for reference clock,
to
D
OUT
(pin 3) of timing LSI
DO (pin 3) of timing LSI; following frequencies ap-
pear on this pin;
At
mode : 9.534964 MHz when CKMD = L level
12.713285 MHz when CKMD = H level
At PAL mode : 9.656250 MHz when CKMD = L level
12.875
) or
27
CLKI
Main clock
MHz when CKMD = H level
28
Vcc
Power supply
Supply +5 V
Phase comparator output for input signals RPI (pin
32) and
(pin 30). When
is Low level. When CPI is delayed, output is High
level, When phases are equal, the terminal imped-
ance is High.
Phase comparator
output
is advanced, output
29
TO
An input pin for comparison horizontal signal to the
phase comparator. Connect to SCHD (pin 33) when
comparator is used. Set to L level when comparator
is not used.
30
Horizontal comparison
input
31
HD
o
Horizontal drive pulse
The pulse occurs at the start of lines. Connect to
timing LSI.
An input pin for the reference horizontal signal to
the phase comparator. Connect to HD (pin 31) when
comparator is used, Set to L level when comparator
is not used.
32
RPI
Horizontal reference
input
A horizontal synchronization pulse obtained by di-
viding 4FSC (pin 43).
At NTSC mode : dividing into 1 /91 O 4FSC.
At PAL mode : dividing into
narily and dividing into 1/1 137
4FSC during one horizontal pe-
riod within the V blanking,
33
SCHD
o
Subcarrier HD
135 4FSC ordi-
The pulse occurs at the start of every field. Con-
nect to VDI (pin 2) of timing
(Pin
of timing
34
VD
0
V drive pulse
) or VDI
The pulse is used for detecting field.
At NTSC mode : 1st field; LOW
2nd field; HIGH
At PAL mode : 1st and 3rd field; LOW
2nd and 4th field; HIGH
35
o
Filed index
36
CPBL
Blanking clamp pulse
When the input is High, BCPI (pin 37) and BCP2
(pin 36) are Low.
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