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參數(shù)資料
| 型號： | LZ93B53 |
| 廠商： | Sharp Corporation |
| 英文描述： | Synchronous Signal Generator for CCD |
| 中文描述： | 同步信號發(fā)生器的防治荒漠化公約 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大小： | 130K |
| 代理商： | LZ93B53 |
PIN FUNCTION
10.
This is a pin to input the clock which is used as
the reference of the horizontal and vertical pulses.
This pin should be connected to DO on the timing
The frequency varies depending on CKMD (pin
5) as follows.
system
270000 pixels fck : 9.534964 MHz(606 fH)
360000 pixels fck : 12.713285
.
system
320000 pixels fck : 9,656250 MHz(6I 8 fH)
420
pixels
: 12.875000 MHz(824 fH)
1
Main clock
G
fH)
2
CLKO
o
Clock out
This is an inverted output pin for CLKI (pin 1).
This is a pin to select TV systems.
G
Low
level
G
High level :
3
ICD
—
TV mode select
system
system
This is a pin to control stop and continuance of
BCPI (pin 10) within the vertical blanking period.
G
High level : BCPI outputs continuous pulses.
G
Low level : BCP
I
stops outputting composite
pulses while there is no effective
pixel within the V blanking period.
4
CPMD
Clamp pulse mode
select
—
This is an input pin to switch the frequency devision
in accordance with the area sensor as follows.
Frequency division
output
5
CKMD
–
Clock mode select
1/3
1/4
CKMD
High
Low
Number of pixels
270000
360000
This is an input pin for the external V reset pulse
which is used to apply vertical synchronization to
the counter (2 fck counter) on the synchronization.
This resetting takes priority over the internal reset-
ting. Since the rise of input at
horizontal synchronous frequency (2 fH) which is two
times as high as the internal frequency, when the
vertical pulses which were separated in terms of
frequency from the composite synchronous signal
from other equipment are used, the fall must have
a phase difference of less than 1/2
with the start timing of the vertical synchronous
signal. When the
synchronization is obtained,
the High level should be selected. The input is de-
signed as a
trigger buffer.
is taken at the
u
6
VRI
Vertical reset
compared
7
–
Test
1
This is an input pin for tests, Typically, this pin
should be open or at the Low level.
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