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參數(shù)資料
| 型號(hào)： | LZ34C10 |
| 廠商： | Sharp Corporation |
| 英文描述： | 1/4-type Color CMOS Image Sensor with 110 k Pixels |
| 中文描述： | 1/4-type彩色CMOS 110萬(wàn)像素圖像傳感器 |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大?。?/td> | 99K |
| 代理商： | LZ34C10 |
LZ34C10
7
TIMING CHART
CLK
ADOUT
(D
0
-D
7
)
Normal
HD
CLK
ADOUT
(D
0
-D
7
)
906
4
363 365
367OBB
OBBOBA
OBA
8
12
16
20
24
28
32
36
40
44
48
52
56
60
64
68
72
76
80
84
889092
HORIZONTAL PULSE TIMING
PHASE RELATIONS BETWEEN DIGITAL OUTPUT (ADOUT) AND CLOCK (CLK)
VERTICAL PULSE TIMING
ππππ
πππππ
Mirror
7
5
3
1
OBB
OBBOBA
OBA
ππππ
πππππ
CLK
ADOUT
(D
0
-D
7
)
Normal
HD
104 108 112 116 120 124 128 132 136 140 144 148 152 156 160 164 168 172 176 180 184 188 192 196 200
OBA
OBAOBB
OBB 2
4
6
8
10
ππππ
Mirror
ADOUT
(D
0
-D
7
)
Normal
Mirror
910
01
HD
SCLK
SDI
AGC
VD
329330
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
SDI, SCLK
Forbidden Period
37 38
OBOB
39
328
289290291
OBOBOBOB
288
D
0
D
10
D
20
D
30
D
38
OBA
OBAOBB
OBB 366 364 362 360 358
ππππ
SYMBOL
t
MIN.
0
TYP.
15
MAX.
40
UNIT
ns
OBOB
3 2 1
OBOBOBOB
4
SERIAL DATA TIMING (SDI, SCLK)
Offset
Shutter
t
The rising edge of the HD pulse must be between two rising edges of CLK (0) and CLK (1).
The falling edge of the HD pulse must be between two rising edges of CLK (78) and CLK (79).
The rising edge and falling edge of the VD pulse must be in high period of the HD pulses.
Data in SDI are taken at the rising edge of SCLK.
Clock frequency of SCLK should be 1/16 of that of CLK.
Do not insert the SDI and SCLK pulses between 36H
*
and 37H
*
. Refer to "
VERTICAL PULSE TIMING
".
Refer to
"SERIAL DATA INPUTS"
for the contents of serial data from D
0
to D
38
.
* It means ordinal number of the HD pulse.
361
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