參數(shù)資料
型號(hào): LZ23H3V1
廠商: Sharp Corporation
英文描述: SOCKET, D, FILTERED, 330PF, 44WAY; Connector type:D Sub, High-Density; Gender:Socket; Ways, No. of:44; Termination method:Solder; Material, contact:Copper Alloy; Plating, contact:Bright Tin; Series:FHTB; Material:Steel; Current RoHS Compliant: Yes
中文描述: 1/3-type隔行彩色CCD傳感器的面積1 090萬像素
文件頁數(shù): 3/20頁
文件大?。?/td> 155K
代理商: LZ23H3V1
LZ23H3V1
3
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Ambient operating temperature
Output transistor drain voltage
Overflow drain clock
Ground
SYMBOL
T
OPR
V
OD
V
OFD
GND
MIN.
TYP.
25.0
15.0
MAX.
UNIT
C
V
V
V
NOTE
14.55
24.5
15.45
26.5
NOTES :
1. Use the circuit parameter indicated in
"SYSTEM CONFIGURATION EXAMPLE"
, and do not connect to DC voltage directly.
2. V
PW
is set below V
VL
that is low level of vertical shift register clock, or is used with the same power supply that is connected
to V
L
of V driver IC.
3. Operation frequency is 14.32 MHz.
4. Operation frequency is 18.00 MHz.
* To apply power, first connect GND and then turn on V
OD
. After turning on V
OD
, turn on PW first and then turn on other powers
and pulses. Do not connect the device to or disconnect it from the plug socket while power is being applied.
1
P-well voltage
V
PW
–10.0
V
VL
V
2
0.0
V
–8.5
–9.0
–9.5
V
V1AL
, V
V1BL
, V
V2L
V
V3AL
, V
V3BL
, V
V4L
V
V1AI
, V
V1BI
, V
V2I
V
V3AI
, V
V3BI
, V
V4I
V
V1AH
, V
V1BH
V
V3AH
, V
V3BH
V
H1L
, V
H2L
V
H1H
, V
H2H
V
RS
f
V1A
, f
V1B
, f
V2
f
V3A
, f
V3B
, f
V4
Vertical shift
register clock
LOW level
INTERMEDIATE level
HIGH level
14.55
0.0
15.0
15.45
V
V
LOW level
HIGH level
p-p level
Horizontal shift
register clock
Reset gate clock
–0.05
4.5
4.5
0.0
5.0
5.0
10.88
13.47
0.05
5.5
5.5
V
V
V
1
3
4
Reset gate clock frequency
f
RS
14.32
18.00
MHz
MHz
3
4
Horizontal shift register clock frequency
f
H1
, f
H2
14.32
18.00
MHz
MHz
3
4
Vertical shift register clock frequency
kHz
kHz
p-p level
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