參數(shù)資料
型號(hào)： LY530ALTR
廠商： STMICROELECTRONICS
元件分類： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PBGA16
封裝： 5 X 5 MM, 1.60 MM HEIGHT, LEAD FREE, LGA-16
文件頁(yè)數(shù)： 10/30頁(yè)
文件大?。?/td> 576K
代理商： LY530ALTR
Digital interfaces
LY530AL
18/30
4.1.1
I2C operation
The transaction on the bus is started through a START (ST) signal. A START condition is
defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After
this has been transmitted by the Master, the bus is considered busy. The next byte of data
transmitted after the start condition contains the address of the slave in the first 7 bits and
the eighth bit tells whether the Master is receiving data from the slave or transmitting data to
the slave. When an address is sent, each device in the system compares the first seven bits
after a start condition with its address. If they match, the device considers itself addressed
by the Master.
The Slave ADdress (SAD) associated to the LY530AL is 110100xb. SDO pin can be used to
modify less significant bit of the device address. If SDO pin is connected to voltage supply
LSb is ‘1’ (address 1101001b) else if SDO pin is connected to ground LSb value is ‘0’
(address 1101000b). This solution permits to connect and address two different gyroscopes
to the same I2C bus.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line
during the acknowledge pulse. The receiver must then pull the data line LOW so that it
remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which
has been addressed is obliged to generate an acknowledge after each byte of data
received.
The I2C embedded inside the LY530AL behaves like a slave device and the following
protocol must be adhered to. After the start condition (ST) a slave address is sent, once a
slave acknowledge (SAK) has been returned, a 8-bit sub-address will be transmitted: the 7
LSb represent the actual register address while the MSB enables address auto increment. If
the MSb of the SUB field is 1, the SUB (register address) will be automatically incremented
to allow multiple data read/write.
The slave address is completed with a Read/Write bit. If the bit was ‘1’ (Read), a repeated
START (SR) condition will have to be issued after the two sub-address bytes; if the bit is ‘0’
(Write) the Master will transmit to the slave with direction unchanged.
Table explains how
the SAD+Read/Write bit pattern is composed, listing all the possible configurations.
Table 12.
SAD+Read/Write patterns
Command
SAD[6:1]
SAD[0] = SDO
R/W
SAD+R/W
Read
110100
0
1
11010001 (39h)
Write
110100
0
11010000 (38h)
Read
110100
1
11010011 (3Bh)
Write
110100
1
0
11010010 (3Ah)
Table 13.
Transfer when Master is writing one byte to slave
Master
ST
SAD + W
SUB
DATA
SP
Slave
SAK
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