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參數(shù)資料
| 型號(hào)： | LX13088CLD |
| 廠商： | MICROSEMI CORP-ANALOG MIXED SIGNAL GROUP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | DUAL SWITCHING CONTROLLER, PDSO10 |
| 封裝： | 3 X 3 MM, ROHS COMPLIANT, PLASTIC, DFN-10 |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 422K |
| 代理商： | LX13088CLD |
LX13088
PRODUCTION DATASHEET
Microsemi
Analog Mixed Signal Group
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 11
Copyright
2010
Rev. 1.1, 2010-06-08
Dual 1A Step-Down Converters
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OPERATION
E/S DECODER LOGIC
The E/S pin serves a dual purpose. It will enable the IC if it
detects either a valid clock signal or a static high logic level. A
static low logic level for longer than 4s is determined to be a
shutdown signal. The decode logic is shown below. The One-
shot function will produce a logic high output (Clock Detect) as
long as the E/S pin is toggling. Clock Detect is used to keep
ENABLE high and to select the E/S clock as the system clock.
If E/S is a static high (non-toggling) input, the retriggerable
one-shot will go low after 4s; this will set Clk Det low and
select the internal oscillator as the system clock.
SYNCHRONIZATION
The converters can be synchronized to an external system
clock present at the E/S input pin. During synchronization, the
converter’s switching frequency will be the frequency of the
external clock, and the two converters will still be 180 degrees
out of phase. The lock in frequency for synchronization is
specified to be between 1.5MHz to 3MHz, minimum sync pulse
width is 100ns.
OVER TEMPERATURE PROTECTION
If an over temperature fault occurs, the DC-DC converter will
stop switching and the SW# outputs will become high
impedance. Note that the temperature fault occurs at a die
temperature of approximately 160C. When the IC cools down,
it will attempt to resume switching. If a POR is activated as a
result of the OT situation, restart will be subject to the soft
start/sequencing routine and will not occur until the OT
condition has been corrected.
The device junction temperature is a function of the device’s
total power dissipation, the junction to ambient thermal
resistance, and the ambient temperature:
(
)
JA
TOTAL
P
A
T
J
T
θ
×
+
=
The total power dissipated by the LX13088 device, PTOTAL,
will be comprised of the power dissipated by the RMS current
flowing through the internal high-side FET during the duty
cycle D time, by the RMS current flowing through the
synchronous rectifier during 1-D time, by the switching or
transitioning of the FET, and of the power dissipated by the
device supply current.
INDUCTOR SELECTION
A 3.3H ±20% inductor is suggested as the internal
compensation has been optimized around this inductor value. A
3.3H is a good compromise, since for an output voltage
ranging from VOUT = 1V to VOUT = 4V, loaded at 1A, the
LIR or the ratio of inductor ripple current to output load will
range from about 20% to 30%, assuming VIN = 5V and the
converter switching at 1.3MHz.
OUTPUT CAPACITOR
To ensure stability and good load transient response, use at
least a 10F output capacitor for converter 1, and a 20F or
greater for converter 2. Output ceramics capacitors with low
ESR are suitable.
SETTING THE OUTPUT VOLTAGE
The LX13088 converter’s maximum duty cycle is
approximately 90%. For a 5V input, 90% duty cycle will be
achieved for an output voltage of about 4V loaded at 1A.
To set the output voltage, connect a resistive divider from the
output to the FBx pin to signal ground. Note that the feedback
voltage is 1.0V. For the desired output voltage VOUT, the
upper resistor from VOUT to FB (RUPPER) is calculated by the
following equation:
×
=
1
VFB
VOUT
LOWER
R
UPPER
R
RLOWER, or the resistor from FBx pin to ground, is selected to be
20k. VFB = 1V, and VOUT is chosen by the designer for the
given application.
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