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參數(shù)資料
| 型號(hào)： | LV8042LG |
| 元件分類(lèi)： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | STEPPER MOTOR CONTROLLER, 0.6 A, PBGA68 |
| 封裝： | 6 X 6 MM, FLGA-68 |
| 文件頁(yè)數(shù)： | 6/15頁(yè) |
| 文件大?。?/td> | 197K |
| 代理商： | LV8042LG |
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LV8042LG
No.A0004-14/29
HOLD (D5) Operation Description
With HOLD (D5) data = “1”, the external CLK data is held as it is in the internal CLK.
In the step hold (1) timing as shown above, the (external) CLK is at “L”, so that the internal CLK is held at “L.”
In the step hold (2) timing, the (external) CLK is at “H”, so that the internal CLK is held at “H.”
With HOLD (D5) data = “0”, the internal CLK is synchronized with the normal (external) CLK.
The output holds the status in the timing of input of step hold. After canceling of step hold, the position No. proceeds
in the timing of CLK (rise).
As long as the hold status continues, the position No. does not proceed even when (external) CLK is input.
Internal logic
(External) CLK
Internal CLK
HOLD(D5)
logic
(External)CLK
HOLD (D5)
1ch output
2ch output
Internal CLK
Held at “L”
0%
Held at “H”
Hold state
Step hold (1)
Step hold cancel
Step hold (2)
Step hold cancel
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