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參數(shù)資料
| 型號： | LV5545DV-FREQ-T1K |
| 廠商： | PLETRONICS INC |
| 元件分類： | XO, clock |
| 英文描述： | CRYSTAL OSCILLATOR, CLOCK, 80 MHz - 325 MHz, LVDS OUTPUT |
| 封裝： | ROHS COMPLIANT, CERAMIC, LCC-6 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大小： | 110K |
| 代理商： | LV5545DV-FREQ-T1K |
LV55D Series 3.3 V
LVDS Clock Oscillators
January 2011
www.pletronics.com
425-776-1880
3
Electrical Specification for 3.30V +
_10% over the specified temperature range and
the frequency range of 80 to 325 MHz
Item
Min
Max
Unit
Condition
Frequency Accuracy “45"
-50
+50
ppm
For all supply voltages, load changes, aging for 1
year, shock, vibration and temperatures
“44"
-25
+25
“20"
-20
+20
Output Waveform
LVDS
Output High Level
--
1.60
Volts
-
See load circuit
R1 = 50 ohms
Output Low Level
0.90
--
Volts
-
Differential Output (V
OD)
250
450
mVolts
-
Output Offset Voltage (V
OS)
1.125
1.375
Volts
> 80 MHz
1.125
1.500
Volts
< 80 MHz
Differential Output Error (dV
OS)--
50
mVolts
-
Output Symmetry
45
55
%
Referenced to 50% of amplitude or crossing point
Output T
RISE and TFALL
300
700
pS
> 80 MHz
Vth is 20% and 80% of waveform
400
900
pS
< 80 MHz
Jitter
-
0.6
pS RMS
Measured from 12KHz to 20MHz from Fnominal
-
2.8
Measured from 10Hz to 1MHz from Fnominal
Vcc Supply Current
-
66
mA
> 80 MHz
Includes current of properly
terminated device
-
45
mA
< 80 MHz
Enable/Disable Internal Pull-up
50
-
Kohm
To Vcc (equivalent resistance)
V disable
-
0.8
Volts
Referenced to Ground
V enable
2.0
-
Volts
Referenced to Ground
Output leakage
V
OUT = VCC
-10
+10
uA
Pad 1 low, device disabled
V
OUT = 0V
-10
+10
uA
Enable
-
10
nS
Time for output to reach a logic state
Disable time
-
10
nS
Time for output to reach a high Z state
Start up time
-
5
mS
> 80 MHz
Measured from the time
Vcc = 3.0V
-
3
mS
< 80 MHz
Operating Temperature Range
-10
+70
oC
Standard Temperature Range
-20
+70
oC
Extended Temperature Range
“C” Option
-40
+85
oC
Extended Temperature Range
“E” Option
Storage Temperature Range
-55
+125
oC
Standby Current I
CC
-3
uA
> 80 MHz
Pad 1 low, device disabled
-
1.5
mA
< 80 MHz
Specifications with Pad 1 E/D open circuit
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