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參數(shù)資料
| 型號： | LV3403M |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO14 |
| 封裝： | MFP-14 |
| 文件頁數(shù)： | 3/3頁 |
| 文件大?。?/td> | 49K |
| 代理商： | LV3403M |
Pin Descriptions
Pin No.Pin nameDescription
1GNDGround.
2VCOM
Common for SCF section. Connect to decoupling capacitor.
3SIG.INSignal input. Input a frequency-modulated signal (composite signal) at 200 to 300 mVrms.
When inputting 76 kHz only, the input sensitivity is 4 mVrms or less.
10MSK OUTMSK output (CMOS output.)
11VREF
Limiter reference pin. Form an LPF with the 10 k
internal resistor and an external
capacitor.
12CLK IN
3.6 MHz clock input. Because the DC bias is output by the limiter amplifier input, the clock
is input with capacitor coupling.
14VCC
Power supply
5, 8, 13TEST PINTest pin. Leave open.
4, 6, 7, 9NCUnused.
Notes on usage:
(1) When using this IC, leave pins 4 to 9 and pin 13 open.
(2) The clock is connected to pin 12 from the decoder (LC72700) clock output pin through a 100 pF capacitor. In addition, by
inserting a resistor in the clock line, it is possible to dampen the rising and falling edges, reducing spurious radiation.
Equivalent Circuit Block Diagram
Note : Pins 4 through 9 and pin 13 must be left open.
No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment,
nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or
indirectly cause injury, death or property loss.
Anyone purchasing any products described or contained herein for an above-mentioned use shall:
1 Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors
and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and
expenses associated with such use:
2 Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO
ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume
production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use
or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of June, 1996. Specifications and information herein are subject to change without notice.
Clock input
MSK output
Dual-mode clock
generator
Bias circuit
SIG. input
76 kHz CW
LV3403M
No.5191-3/3
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