參數(shù)資料
型號: LV23401V
廠商: SANYO SEMICONDUCTOR CO LTD
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PDSO30
封裝: 0.275 INCH, SSOP-30
文件頁數(shù): 4/24頁
文件大?。?/td> 594K
代理商: LV23401V
LV23401V
Interface specification
1) LV23401 Interface specification
LV23401 is controlled by the C2B (Computer Control Bus) cereal bus format.
C2B is a bus to achieve it economically surely format as for the communications between LSI in the system with two or
more LSI. Because it is single master's system, the processing of a complex arbitration is unnecessary. Therefore, the
load of hardware is reduced, and the system configuration that is economically abundant becomes possible.
Moreover, neither a lot of kinds of controller and interface doing nor special hardware is easily needed by serial I/O
with software. C2B is thought between LSI in the equipment, and the communications between equipment that need a
long line are not targeted.
2) C2B data composition
DI control data (cereal data input) composition
IN mode
B0
0
B1
0
B2
0
B3
0
A0
0
A1
0
A2
1
A3
1
DI
Address
D0
D1
D2
D3
D4
D5
D6
D7
R0
R1
R2
R3
R4
R5
R6
R7
Data
Resister
LV23401V is controlled by the bus format composed of the sub-address (register) that stores the data of the device
address of 8bit (address) and each 8bit. "C0" is input from LSB to the start as an address when the serial data is input to
LV23401V, the device that controls is specified, and the mode as the data input is fixed. It inputs from LSB in order of
data (bit setting)→ register synchronizing with data clock (CL) after the address is input and the data input can be
concluded.
Composition of the DO control data (serial data output)
OUT mode
B0
1
B1
0
B2
0
B3
0
A0
0
A1
0
A2
1
A3
1
DI
Address
R00_B0
R00_B1
R00_B2
R00_B3
R00_B4
R00_B5
R00_B6
R00_B7
Reg00h
Data
DO
R01_B0
R01_B1
R01_B2
R01_B3
R01_B4
R01_B5
R01_B6
R01_B7
R02_B0
R02_B1
R02_B2
R02_B3
R02_B4
R02_B5
R03_B6
R03_B7
Reg01h
Data
Reg02h
Data
"C1" is input from LSB to the start as an address when the serial data is output from LV23401V, the controlled device
is specified, and the mode as the data output is fixed. The subsequent data is output from DO pin synchronizing with
lock (CL) after the address is input LSB from one with small register number. The output of data is ended by setting CE
pin to Low.
No.A1746-12/24
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