參數(shù)資料
型號: LV23100V
廠商: SANYO SEMICONDUCTOR CO LTD
元件分類: 調(diào)諧器
英文描述: 2-BAND, AUDIO TUNER, PDSO36
封裝: 0.275 INCH, SSOP-36
文件頁數(shù): 9/12頁
文件大小: 312K
代理商: LV23100V
LV23100V
No.8370-6/12
Continued from preceding page.
No.
Control block data
Description
Related data
(9)
DO pin
control data
DOC0
DOC1
DOC2
Data to determine the output of the DO pin.
DOC2
DOC1
DOC0
DO pin condition
0
1
0
1
0
1
Open
Low when unlock is detected.
end-UC (See the item with asterisk below)
Open
1
0
1
0
1
0
1
Open
Low when stereo
Low when SDON
Open
The open condition is selected at power ON/reset.
* IF counter counting end check
With end-UC set and IF counter starting (CTE = 0
→1), DO pin opens automatically.
At end of counting of the IF counter, DO pin goes LOW and check on counting end can be made.
DO pin opens when serial data is entered/output (CE pin : Hi)
Note : DO pin is always in the open condition during data input (IN1 and IN2 modes, during CE : Hi
period), regardless of DO pin control data (DOC0 to 2). In the DO pin condition during data output
(OUT mode, CE-Hi period), the content of internal DO serial data is output in synchronization with
CL, regardless of DO pin control data (DOC).
UL0, UL1
CTE
(10)
Unlock detection
data
UL0, UL1
Phase error (φE) detection width selection data to judge if PLL is locked.
Phase error exceeding the detection width is judged that PLL is locked
(* : don’t care)
UL1
UL0
φE Detection width
Detection output
0
1
0
1
*
Stop
0
±6.67s
Open
Direct output of
φE
φE extended by 1 to 2 ms
* DO pin is LOW. Serial data output : UL = 0.
DOC0
DOC1
DOC2
(11)
Phase
comparator
control data
DZ
Data to control the dead zone of phase comparator
DZ
Charge pump output
0
1
DZA
DZB
Dead zone width : DZA<DZB
(12)
Charge pump
control data
DLC
Data to enforce control of charge pump output
DLC
Charge pump output
0
1
Normal
Forced to LOW
In case of dead lock because of VCO oscillation stop when the VCO control voltage (Vtune) is 0V,
it is possible to clear dead lock by setting the charge pump output to LOW and V tune to VCC.
(Dead lock clear circuit)
(13)
LSI test data
TEST0 to 2
LSI test data
TEST0
TEST1
All to be set to “0”
TEST2
All set to zero at power ON/reset
~
Counting start
DO pin
1
Counting end
2
CE : HI
3
~
~ ~
1
2
3
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