參數(shù)資料
型號(hào): LV23000M
元件分類: 接收器
英文描述: AM/FM, AUDIO SINGLE CHIP RECEIVER, PDSO36
封裝: 0.375 INCH, MFP-36
文件頁(yè)數(shù): 12/14頁(yè)
文件大?。?/td> 144K
代理商: LV23000M
No. 6903-7/14
LV23000M
Continued from preceding page.
No.
Control block/data
Description
Related data
Controls the phase comparator dead band.
(8)
Phase comparator
control data
DZ0, DZ1
(12)
IC test data
TEST0 toTEST2
Sets the outputs from the BO1 and BO2 output ports.
Data = 0: Open
= 1: Low
IC test data
TEST0
TEST1
All bits must be set to 0.
TEST2
All these bits are set to 0 after the power on reset.
(9)
Output port data
BO1, BO2
If deadlock occurs due to VCO oscillation when the VCO control voltage (Vtune) is 0 V, the
deadlock can be released by setting the charge pump output low and setting Vtune to VCC.
(This is referred to as a deadlock clear circuit.)
Determines the outputs of the SDC0 and SDC1 ports and sets the SD sensitivity.
(15)
(16)
SD sensitivity
adjustment data
SDC0
SDC1
DZ1
DZ0
Dead band mode
0
DZA
0
1
DZB
1
0
DZC
1
DZD
Dead band widths: DZA < DZB < DZC < DZD
Forcibly controls the state of the charge pump output.
DLC
Charge pump output
0
Normal operation
1
Forced to the low level.
(10)
Charge pump
control data
DLC
This bit should normally be set to 1. However, setting this bit to 0 sets the device to
degraded input sensitivity mode, and the input sensitivity is reduced by about 10 to
30 mV rms.
(11)
IFS
(13)
DNC
This bit must be set to 0.
(14)
Forced mono
control data
STSW
Determines the output of the STSW output port and controls the forced stereo function.
Data = 0: Mono
= 1: Stereo
SDC0
SDC1
SD sensitivity (typ)
0
42 dBV
0
1
45 dBV
1
0
51 dBV
1
56 dBV
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