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參數(shù)資料
| 型號(hào)： | LUCW3000CCN-TR |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 2200 MHz, PDSO14 |
| 封裝： | TSSOP-14 |
| 文件頁數(shù)： | 7/28頁 |
| 文件大小： | 326K |
| 代理商： | LUCW3000CCN-TR |
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Advance Data Sheet
December 1999
W3000 PLL Dual-Band Frequency Synthesizer
Lucent Technologies Inc.
15
MAIN Register
The MAIN register is intended for programming that can occur frequently for dynamic channel switching and
putting the W3000 into power-saving mode.
Table 18. MAIN Register Bit Description (C0 = 0, C1 = 0)
Bit
Name
Description
1
C0 = 0
Register address bit. C0 = 0 for MAIN (last bit in serial sequence).
2:8
A[1:7]
Swallow counter for prescaler modulus control.
9:19
M[1:11]
Main counter.
20
Reserved
—
21
Reserved
—
22
EN2
Enable all PLL circuits (0 = powerdown mode).
23
B
Band select for charge pump current control (band 1 = 0, band 2 = 1).
24
C1 = 0
Secondary address bit.
Table 19. MAIN Register
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
C0
= 0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
M
1
M
2
M
3
M
4
M
5
M
6
M
7
M
8
M
9
M
10
M
11
X
EN
B
C1
= 0
Note: X bits are don’t care bits.
Table 20. A1:A7: Swallow Counter Count (Bits 2 to 8)
A7
Bit 8
A6
Bit 7
A5
Bit 6
A4
Bit 5
A3
Bit 4
A2
Bit 3
A1
Bit 2
Counter Ratio
0
1
0
1
0
2
.
0
1
63
.
1
127
Last bit in serial sequence
First bit in serial sequence
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