參數(shù)資料
型號: LU6612
廠商: Lineage Power
英文描述: Single-FET for 10Base-T/100Base-TX(應用于10基數(shù)-T和100基數(shù)-TX 的單快速以太網(wǎng)收發(fā)器)
中文描述: 單為10BASE-T/100BASE-TX快速以太網(wǎng)場效應晶體管(應用于10基數(shù)- T的和100基數(shù),得克薩斯州的單快速以太網(wǎng)收發(fā)器)
文件頁數(shù): 25/36頁
文件大?。?/td> 528K
代理商: LU6612
Lucent Technologies Inc.
25
Data Sheet
July 2000
LU6612
FASTCAT Single-FET for 10Base-T/100Base-TX
Timing Characteristics (Preliminary)
Table 25. MII Management Interface Timing (25 pF Load)
* When operating MDC above 6.25 MHz, MDC must be synchronous with LSCLK and have a setup time of 15 ns and a hold time of 5 ns,
with respect to LSCLK.
5-4959(F).a
Figure 6. MDIO Input Timing
5-4960(F).c
Figure 7. MDIO Output Timing
5-5312(F).r1
Note: MDIO turnaround (TA) time is a 2-bit time spacing between the register address field, and the data field of a frame to avoid drive conten-
tion on MDIO during a read transaction. During a write to the LU6612, these bits are driven to a 10 by the station. During a read, the
MDIO is not driven during the first bit time and is driven to a 0 by the LU6612 during the second bit time.
Figure 8. MDIO During TA (Turnaround) of a Read Transaction
Name
t1
t2
t3
t4
t5
t6
Parameter
Min
10
10
0
40
80
Typ
200
200
400
Max
40
Unit
ns
ns
ns
ns
ns
ns
MDIO Valid to Rising Edge of MDC (setup)
Rising Edge of MDC to MDIO Invalid (hold)
MDC Falling Edge to MDIO Valid (prop. delay)
MDC High*
MDC Low*
MDC Period*
MDC
MDIO
t1
t2
MDC
MDIO
t5
t4
t6
t3
MDC
MDIO
< R >
< Z >
< O >
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