參數(shù)資料
型號(hào)： LU3X54FTL-HS208-DB
英文描述： QUAD-FET for 10Base-T/100Base-TX/FX
中文描述： 四核10Base-T/100Base-TX/FX場(chǎng)效應(yīng)管
文件頁數(shù)： 6/54頁
文件大?。?/td> 677K
代理商： LU3X54FTL-HS208-DB
6
Lucent Technologies Inc.
LU3X54FT
QUAD-FET for 10Base-T/100Base-TX/FX
Data Sheet
July 2000
Description
(continued)
Clocking
(continued)
Either the on-chip 20 MHz clock synthesizer (default
clock) can be used, or H-DUPLED[A]/CLK20_SEL
(pin 198) can be pulled high (sensed on powerup and
reset) to select the external 20 MHz clock input.
The crystal specifications for the device are listed in
Table 1, and the crystal circuit is shown in Figure 3 and
Figure 4.
Table 1. LU3X54FT Crystal Specifications
FX Mode
Each individual port of the LU3X54FT can be operated
in 100Base-FX mode by selecting it through the pin
program option (RXLED[D:A]/FX_MODE_EN[D:A], or
through the register bit (register 29, bit 0). FX mode
can operate in full or half duplex. Each individual chan-
nel’s duplex can be set by register zero bit eight (0.8) or
all ports duplex can be hardware configured at power
up or rest by pin 201 FULL_DUP
When operating in FX mode, the twisted-pair I/O pins
are reused as the fiber-optic transceiver I/O data pins,
and the fiber-optic signal detect (FOSD) inputs are
enabled.
Figure 4 shows a typical FX port interface. Note that no
additional external components, excluding those
needed by the fiber transceiver, are required.
When a port is placed in FX mode, it will automatically
configure the port for 100Base-FX operation (and the
register bit control will be ignored) such that:
I
The far-end fault signaling option will be enabled.
I
The MLT-3 encoding/decoding will be disabled.
I
Scrambler/descrambler will be disabled.
I
Autonegotiation will be disabled.
I
The signal detect inputs will be activated.
I
10Base-T will be disabled.
Parameter
Requirement
Type
Frequency
Stability
Shunt Capacitor
Load Capacitor
Series Resistance
Quartz Fundamental Mode
25 MHz
±25 ppm, 0 °C—70 °C
7 pF
20 pF
<30
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