參數(shù)資料
型號(hào): LU3X31T-T64
廠商: Lineage Power
英文描述: Single-Port 3 V 10/100 Ethernet Transceiver TX/FX(單端口 3 V 10M位和100M位以太網(wǎng)收發(fā)器)
中文描述: 單端口3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯(單端口3伏1000萬位和100米位以太網(wǎng)收發(fā)器)
文件頁(yè)數(shù): 28/44頁(yè)
文件大?。?/td> 580K
代理商: LU3X31T-T64
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Preliminary Data Sheet
July 2000
28
Lucent Technologies Inc.
Table 22. Config 100 Register (Register 18h)
0
LED Pulse Stretching Disable 1
LED pulse stretching disabled.
0
LED pulse stretching enabled.
When pulse stretching is enabled, all LED
outputs are stretched to 48 ms—72 ms.
R/W
0
Bit(s)
15
Name
BPSCR
Description
R/W
R/W
Default
Pin
1
Disable scrambler/descrambler.
0
Enable scrambler/descrambler.
This bit is initialized to the logic level of
BPSCR pin (pin 41) at powerup or reset.
1
Disable 4B/5B encoder/decoder.
0
Enable 4B/5B encoder/decoder.
This bit is initialized to the logic level of
BP4B5B pin (pin 42) at powerup or reset.
Reserved.
1
Pass unaligned data to MII.
0
Pass aligned data to MII.
This bit is initialized to the logic level of
BPALIGN pin (pin 44) at powerup or reset.
Reserved.
1
Force good link in 100 Mbits/s mode.
0
Normal operation.
Reserved.
1
Passes HALT symbols to the MII.
0
Normal operation.
1
Loads the scrambler seed.
0
Normal operation.
Setting this bit loads the user seed stored
in register 19h into the 100Base-X scram-
bler. The content of this bit returns to 0
after the loading process is completed and
no transmit is active.
1
Burst mode.
0
Normal operation.
Setting this bit expands the 722
μ
s scram-
bler time-out period to 2,000
μ
s.
Reserved.
14
BP4B5B
R/W
Pin
13
12
Reserved
BPALIGN
RO
R/W
0h
Pin
11:10
9
Reserved
RO
R/W
0h
0h
Force Good Link 100
8:6
5
Reserved
Accept Halt
RO
R/W
0h
0h
4
Load Seed
R/W, SC
0h
3
Burst Mode
R/W
0h
2:0
Reserved
RO
0h
Bit(s)
Name
Description
R/W
Default
MII Registers
(continued)
Table 21. PHY Control/Status Register (Register 17h)
(continued)
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