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參數(shù)資料
| 型號： | LTUY |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 1-/2-Channel 20-Bit UPower No Latency ADCs in MSOP-10 |
| 中文描述： | 1-/2-Channel 20位ADC的無延遲UPower采用MSOP - 10 |
| 文件頁數(shù)： | 12/32頁 |
| 文件大?。?/td> | 375K |
| 代理商： | LTUY |
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12
LTC2421/LTC2422
24212f
APPLICATIOU
fault current, a resistor of up to 5k may be added in series
with the V
IN
pin without affecting the performance of the
device. In the physical layout, it is important to maintain
the parasitic capacitance of the connection between this
series resistance and the V
IN
pin as low as possible; there-
fore, the resistor should be located as close as practical to
the V
IN
pin. The effect of the series resistance on the con-
verter accuracy can be evaluated from the curves pre-
sented in the Analog Input/Reference Current section. In
addition, a series resistor will introduce a temperature de-
pendent offset error due to the input leakage current. A
1nA input leakage current will develop a 1ppm offset error
on a 5k resistor if V
REF
= 5V. This error has a very strong
temperature dependency.
W
U
U
Figure 4. Output Data Timing
Output Data Format
The LTC2421/LTC2422 serial output data stream is 24 bits
long. The first 4 bits represent status information indicat-
ing the sign, selected channel, input range and conversion
state. The next 20 bits are the conversion result, MSB first.
Bit 23 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 22 (second output bit) for the LTC2422, this bit is LOW
if the last conversion was performed on CH0 and HIGH for
CH1. This bit is always LOW for the LTC2421.
Bit 21 (third output bit) is the conversion result sign indi-
cator (SIG). If V
IN
is >0, this bit is HIGH. If V
IN
is <0, this
bit is LOW. The sign bit changes state during the zero code.
Bit 20 (fourth output bit) is the extended input range (EXR)
indicator. If the input is within the normal input range
0
≤
V
IN
≤
V
REF
, this bit is LOW. If the input is outside the
normal input range, V
IN
> V
REF
or V
IN
< 0, this bit is HIGH.
The function of these bits is summarized in Table 1.
Table 1. LTC2421/LTC2422 Status Bits
Bit 23
EOC
0
0
0
0
Bit 22
CH0/CH1
*0/1
*0/1
*0/1
*0/1
Bit 21
SIG
1
1
1/0
0
Bit 20
EXR
1
0
0
1
Input Range
V
IN
> V
REF
0 < V
IN
≤
V
REF
V
IN
= 0
+
/0
–
V
IN
< 0
*Bit 22 displays the channel number for the LTC2422. Bit 22 is always
0 for the LTC2421
Bit 19 (fifth output bit) is the most significant bit (MSB).
Bits 19-0 are the 20-bit conversion result MSB first.
Bit 0 is the least significant bit (LSB).
Data is shifted out of the SDO pin under control of the serial
clock (SCK), see Figure 4. Whenever CS is HIGH, SDO
remains high impedance and any SCK clock pulses are
ignored by the internal data out shift register.
In order to shift the conversion result out of the device, CS
must first be driven LOW. EOC is seen at the SDO pin of the
device once CS is pulled LOW. EOC changes real time from
HIGH to LOW at the completion of a conversion. This sig-
nal may be used as an interrupt for an external microcon-
troller. Bit 23 (EOC) can be captured on the first rising edge
of SCK. Bit 22 is shifted out of the device on the first falling
edge of SCK. The final data bit (Bit 0) is shifted out on the
falling edge of the 23rd SCK and may be latched on the
rising edge of the 24th SCK pulse. On the falling edge of the
24th SCK pulse, SDO goes HIGH indicating a new conver-
sion cycle has been initiated. This bit serves as EOC (Bit
23) for the next conversion cycle. Table 2 summarizes the
output data format.
MSB
EXT
SIG
CH0/CH1
1
2
3
4
5
19
20
24
BIT 0
BIT 19
BIT 4
LSB
20
BIT 20
BIT 21
BIT 22
SDO
SCK
CS
EOC
BIT 23
SLEEP
DATA OUTPUT
CONVERSION
24212 F04
Hi-Z
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