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參數(shù)資料
型號: LTM9009CY-14#PBF
廠商: Linear Technology
文件頁數(shù): 10/40頁
文件大?。?/td> 0K
描述: IC ADC 14BIT UMODULE 140BGA
標準包裝: 210
系列: µModule®
位數(shù): 14
采樣率(每秒): 80M
數(shù)據(jù)接口: Serial LVDS
轉換器數(shù)目: 8
功率耗散(最大): 997mW
電壓電源: 模擬和數(shù)字
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 140-BFBGA
供應商設備封裝: 140-BGA(11.25x9)
包裝: 托盤
輸入數(shù)目和類型: 8 Differential; 8 Single-Ended
LTM9011-14/
LTM9010-14/LTM9009-14
18
9009101114fa
pin FuncTions
AIN1+ (B2): Channel 1 Positive Differential Analog Input.
AIN1– (B1): Channel 1 Negative Differential Analog Input.
VCM12 (B3): Common Mode Bias Output, Nominally Equal
to VDD/2. VCM should be used to bias the common mode
of the analog inputs of channels 1 and 2. VCM is internally
bypassed to ground with a 0.1F ceramic capacitor. No
external capacitance is required.
AIN2+ (C2): Channel 2 Positive Differential Analog Input.
AIN2– (C1): Channel 2 Negative Differential Analog Input.
AIN3+ (E2): Channel 3 Positive Differential Analog Input.
AIN3– (E1): Channel 3 Negative Differential Analog Input.
VCM34 (F3): Common Mode Bias Output, Nominally Equal
to VDD/2. VCM should be used to bias the common mode
of the analog inputs of channels 3 and 4. VCM is internally
bypassed to ground with a 0.1F ceramic capacitor. No
external capacitance is required.
AIN4+ (G2): Channel 4 Positive Differential Analog Input.
AIN4– (G1): Channel 4 Negative Differential Analog Input.
AIN5+ (H1): Channel 5 Positive Differential Analog Input.
AIN5– (H2): Channel 5 Negative Differential Analog Input.
VCM56 (J3): Common Mode Bias Output, Nominally Equal
to VDD/2. VCM should be used to bias the common mode
of the analog inputs of channels 5 and 6. VCM is internally
bypassed to ground with a 0.1F ceramic capacitor. No
external capacitance is required.
AIN6+ (K1): Channel 6 Positive Differential Analog Input.
AIN6– (K2): Channel 6 Negative Differential Analog Input.
AIN7+ (M1): Channel 7 Positive Differential Analog Input.
AIN7– (M2): Channel 7 Negative Differential Analog Input.
VCM78 (N3): Common Mode Bias Output, Nominally Equal
to VDD/2. VCM should be used to bias the common mode
of the analog inputs of channels 7 and 8. VCM is internally
bypassed to ground with a 0.1F ceramic capacitor. No
external capacitance is required.
AIN8+ (N1): Channel 8 Positive Differential Analog Input.
AIN8– (N2): Channel 8 Negative Differential Analog Input
VDD (D3, D4, E3, E4, K3, K4, L3, L4): 1.8V Analog Power
Supply. VDD is internally bypassed to ground with 0.1μF
ceramic capacitors.
ENC+ (P5): Encode Input. Conversion starts on the rising
edge.
ENC(P6): Encode Complement Input. Conversion starts
on the falling edge.
CSA (L5): In serial programming mode, (PAR/SER = 0V),
CSA is the serial interface chip select input for registers
controlling channels 1, 4, 5 and 8. When CS is low, SCK
is enabled for shifting data on SDI into the mode control
registers.Inparallelprogrammingmode(PAR/SER=VDD),
CS selects 2-lane or 1-lane output mode. CS can be driven
with 1.8V to 3.3V logic.
CSB (M5): In serial programming mode, (PAR/SER = 0V),
CSB is the serial interface chip select input for registers
controlling channels 2, 3, 6 and 7. When CS is low, SCK
is enabled for shifting data on SDI into the mode control
registers.Inparallelprogrammingmode(PAR/SER=VDD),
CS selects 2-lane or 1-lane output mode. CS can be driven
with 1.8V to 3.3V logic.
SCK (L6): In serial programming mode, (PAR/SER =
0V), SCK is the serial interface clock input. In parallel
programming mode (PAR/SER = VDD),SCKselects3.5mA
or 1.75mA LVDS output currents. SCK can be driven with
1.8V to 3.3V logic.
SDI (M6): In serial programming mode, (PAR/SER = 0V),
SDIistheserialinterfacedataInput.DataonSDIisclocked
into the mode control registers on the rising edge of SCK.
In parallel programming mode (PAR/SER = VDD), SDI can
be used to power down the part. SDI can be driven with
1.8V to 3.3V logic.
GND (See Pin Configuration Table): ADC Power Ground.
Use multiple vias close to pins.
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