V+ DIV C1 0.1F R1 R2
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    參數(shù)資料
    型號(hào): LTC6994CS6-2#TRPBF
    廠商: Linear Technology
    文件頁數(shù): 13/26頁
    文件大?。?/td> 0K
    描述: IC DELAY LINE TSOT-23-6
    產(chǎn)品培訓(xùn)模塊: TimerBlox Family Timing Devices
    產(chǎn)品目錄繪圖: LTC699_TSOT-23
    特色產(chǎn)品: TimerBlox?
    標(biāo)準(zhǔn)包裝: 2,500
    系列: TimerBlox®
    功能: 可編程
    可用的總延遲: 1µs ~ 33.6s
    獨(dú)立延遲數(shù): 1
    電源電壓: 2.25 V ~ 5.5 V
    工作溫度: -40°C ~ 85°C
    安裝類型: 表面貼裝
    封裝/外殼: SOT-23-6 細(xì)型,TSOT-23-6
    供應(yīng)商設(shè)備封裝: TSOT-23-6
    包裝: 帶卷 (TR)
    配用: DC1562A-E-ND - BOARD EVAL LTC6992-3
    LTC6994-1/LTC6994-2
    20
    699412fb
    699412 F16
    LTC6994
    IN
    GND
    SET
    OUT
    V+
    DIV
    C1
    0.1F
    R1
    R2
    RSET
    V+
    DIV
    SET
    OUT
    GND
    IN
    C1
    R1
    R2
    V+
    RSET
    DCB PACKAGE
    IN
    GND
    SET
    OUT
    V+
    DIV
    R2
    V+
    RSET
    TSOT-23 PACKAGE
    R1
    C1
    applicaTions inForMaTion
    Figure 16. Supply Bypassing and PCB Layout
    Supply Bypassing and PCB Layout Guidelines
    TheLTC6994isanaccuratemonostablemultivibratorwhen
    used in the appropriate manner. The part is simple to use
    and by following a few rules, the expected performance is
    easily achieved. Adequate supply bypassing and proper
    PCB layout are important to ensure this.
    Figure 16 shows example PCB layouts for both the SOT-23
    and DCB packages using 0603 sized passive components.
    The layouts assume a two layer board with a ground plane
    layer beneath and around the LTC6994. These layouts are
    a guide and need not be followed exactly.
    1. Connect the bypass capacitor, C1, directly to the V+ and
    GND pins using a low inductance path. The connection
    from C1 to the V+ pin is easily done directly on the top
    layer. For the DCB package, C1’s connection to GND is
    also simply done on the top layer. For the SOT-23, OUT
    can be routed through the C1 pads to allow a good C1
    GND connection. If the PCB design rules do not allow
    that,C1’sGNDconnectioncanbeaccomplishedthrough
    multiple vias to the ground plane. Multiple vias for both
    the GND pin connection to the ground plane and the
    C1 connection to the ground plane are recommended
    to minimize the inductance. Capacitor C1 should be a
    0.1F ceramic capacitor.
    2. Place all passive components on the top side of the
    board. This minimizes trace inductance.
    3. Place RSET as close as possible to the SET pin and make
    adirect,shortconnection.TheSETpinisacurrentsum-
    ming node and currents injected into this pin directly
    modulate the output delay. Having a short connection
    minimizes the exposure to signal pickup.
    4. Connect RSET directly to the GND pin. Using a long path
    or vias to the ground plane will not have a significant
    affect on accuracy, but a direct, short connection is
    recommended and easy to apply.
    5. Use a ground trace to shield the SET pin. This provides
    another layer of protection from radiated signals.
    6. Place R1 and R2 close to the DIV pin. A direct, short
    connection to the DIV pin minimizes the external signal
    coupling.
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