參數(shù)資料
型號(hào)： LTC6909HMS#PBF
廠商： Linear Technology
文件頁(yè)數(shù)： 3/22頁(yè)
文件大?。?/td> 0K
描述： IC OSC SILICON 6.67MHZ 16-MSOP
標(biāo)準(zhǔn)包裝： 37
類(lèi)型： 振蕩器 - 硅
頻率： 12.5kHz ~ 6.67MHz
電源電壓： 2.7 V ~ 5.5 V
電流 - 電源： 2.4mA
工作溫度： -40°C ~ 125°C
封裝/外殼： 16-TFSOP（0.118"，3.00mm 寬）
包裝： 管件
供應(yīng)商設(shè)備封裝： 16-MSOP
安裝類(lèi)型： 表面貼裝
LTC6909
11
6909fa
Spread Spectrum Frequency Modulation
The LTC6909 can operate with spread spectrum frequency
modulation(SSFM).Inthismode,theoscillator’sfrequency
is modulated by a pseudorandom noise (PRN) signal
to spread the oscillator’s energy over a wide frequency
band. This spreading decreases the peak electromagnetic
radiationlevelsandimproveselectromaneticcompatibility
(EMC) performance.
Theamountoffrequencyspreadingisfixedat20%(±10%),
where frequency spreading is defined as:
Frequency Spreading (in %) = 100 (fMAX – fMIN)/fOUT
The IMASTER current is a dynamic signal generated by
a multiplying digital-to-analog converter (MDAC) refer-
enced to ISET and lowpass filtered. IMASTER varies in a
psuedorandom noise-like manner between 0.9 ISET and
1.1 ISET. This causes the output frequency to vary in a
pseudorandom noise-like manner between 0.9 fOUT and
1.1 fOUT.
To disable the SSFM, connect one of the active outputs
to the MOD pin. An AC detector circuit shuts down the
modulation circuitry if a frequency in the vicinity of the
output frequency is detected at the MOD pin.
As stated previously, the modulating waveform is a pseu-
dorandomnoise-likewaveform.Thepseudorandomsignal
is generated by a linear feedback shift register that is 15
bits long. The pseudorandom sequence will repeat every
(215 – 1) N clock cycles. This guarantees a repetition
rate below 13Hz for output frequencies up to 6.67MHz.
Seven bits of the shift register are sent in parallel to the
MDAC which produces the modulating current waveform.
Being a digitally generated signal, the output of the MDAC
is not a perfectly smooth waveform, but consists of (27)
discrete steps that change every shift register clock cycle.
Note that the shift register clock is the output frequency,
fOUT, divided by N, where N is the modulation rate divider
setting, which is determined by the state of the MOD pin.
The MOD pin should be tied to ground for the N = 16 set-
ting. Floating the MOD pin selects N = 32. The MOD pin
should be tied to V+ for the N = 64 setting.
The output of the MDAC is then filtered by a lowpass filter
withacornerfrequencysettothemodulationrate(fOUT/N).
This limits the rate of frequency change and softens the
corners of the frequency control signal, but allows the
waveform to fully settle at each frequency step. The rise
and fall times of this single pole filter are approximately
0.35/fCORNER. This is beneficial for clocking switching
regulators, as discussed in the Applications Information
section. Figure 3 illustrates how the output frequency
varies over time.
Figure 3
operAtion
tREPEAT = ((215 – 1) N)/fOUT
tSTEP = N/fOUT
fOUT + 10%
128 STEPS
tREPEAT
tSTEP
fOUT – 10%
TIME
FREQUENCY
6909 F03
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