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參數(shù)資料
| 型號(hào)： | LTC4361CTS8-2#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8 |
| 封裝： | LEAD FREE, PLASTIC, MO-193, TSOT-23, 8 PIN |
| 文件頁數(shù)： | 15/16頁 |
| 文件大?。?/td> | 327K |
| 代理商： | LTC4361CTS8-2#TRPBF |
LTC4361-1/LTC4361-2
8
436112fa
APPLICATIONS INFORMATION
The LTC4361-1 has an internal latch that maintains this
off state until it is reset. To reset this latch, cycle IN be-
low 2.1V (VIN(UVL)) or ON above 1.5V (VON(TH)) for more
than 500μs. After reset, the LTC4361-1 goes through the
start-up cycle.
In applications not requiring the overcurrent protection, tie
the SENSE pin to the IN pin. To implement an overcurrent
threshold ITRIP, choose RSENSE using the formula:
RSENSE =
ΔV
OC
ITRIP
After choosing the RSENSE, keep in mind that:
ITRIP(MAX) =
ΔV
OC(MAX)
RSENSE(MIN)
ITRIP(MIN) =
ΔV
OC(MIN)
RSENSE(MAX)
PWRGD Output
PWRGD is an active low output with a MOSFET pull-down
to ground and a 500k resistive pull-up to OUT. The PWRGD
pin pull-down releases during the low current sleep mode
(invoked by ON high), UVLO, overvoltage or overcurrent
and the subsequent 130ms start-up delay. After the start-
up delay, GATE starts its slow ramp-up and control of the
PWRGDpull-downpassesontotheGATEhighcomparator.
VGATE > VGATE(TH) for more than 65ms asserts the PWRGD
pull-down and VGATE < VGATE(TH) releases the pull-down.
The PWRGD pull-down is capable of sinking up to 3mA
of current allowing it to drive an optional LED. To inter-
face PWRGD to another I/O rail, connect a resistor from
PWRGD to the I/O rail with a resistance low enough to
override the internal 500k pull-up to OUT. Figure 2 details
PWRGD behavior for a LTC4361-2 with 1k pull-up to 5V
at PWRGD.
IN
OUT
GATE
ON
PWRGD
VGATE(TH)
VIN(UVL)
ICABLE
OC
THRESHOLD
10μs (NOT TO SCALE)
436112 F02
VIN(OV)– VOV
START-UP
FROM UVLO
RESTART
FROM OV
OV
RESTART
FROM ON
ON
RESTART
FROM OC
OC
VIN(OV)
130ms
65ms
130ms
65ms
130ms
65ms
130ms
65ms
Figure 2. PWRGD Behavior
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