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參數(shù)資料
| 型號： | LTC4352CMS#PBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO12 |
| 封裝： | LEAD FREE, PLASTIC, MSOP-8 |
| 文件頁數(shù)： | 16/16頁 |
| 文件大?。?/td> | 194K |
| 代理商： | LTC4352CMS#PBF |
LTC4352
9
4352f
Figure 3. Start-up Waveform for Single MOSFET Application
VOLTAGE
(5V/DIV)
TIME (2.5ms/DIV)
4352 FO3
CPO
GATE
OUT
VIN, SOURCE
VCC
VIN = 5V
C2 = 0.1μF
APPLICATIONS INFORMATION
N-channel MOSFETs. The maximum allowable drain-
source voltage, BVDSS, must be higher than the supply
voltages as the full supply voltage can appear across the
MOSFET when the input falls to 0V.
The FAULT pin pulls low to signal an open MOSFET fault
whenever the forward voltage drop across the enhanced
MOSFET exceeds 250mV. The RDS(ON) should be small
enough to conduct the maximum load current while not
triggering such a fault (when using FAULT), and to stay
within the MOSFET’s power rating at the maximum load
current.
CPO Capacitor Selection
The recommended value of the capacitor between the
CPO and SOURCE pins is approximately 10x the input
capacitance, CISS, of the MOSFET. A larger capacitor takes
a correspondingly longer time to charge up by the internal
charge pump. A smaller capacitor suffers more voltage
drop during a fast gate turn-on event as it shares charge
with the MOSFET gate capacitance.
CPO and GATE Start-Up
In single MOSFET applications, CPO is initially pulled up
to a diode below the SOURCE pin (Figure 3). In back-to-
back MOSFET applications, CPO starts off at 0V, since
SOURCE is near ground (Figure 4). CPO starts ramping
up 10μs after VCC clears its undervoltage lockout level.
Another 40μs later, GATE will also start ramping up with
CPO if UV, OV and VIN – OUT conditions allow it to. The
ramp rate is decided by the CPO pull-up current into the
combined CPO and GATE pin capacitances. An internal
clamp limits the CPO voltage to 6.7V above SOURCE, while
the nal GATE voltage is determined by the forward drop
servo amplier.
MOSFET Selection
The LTC4352 drives N-channel MOSFETs to conduct the
load current. The important features of the MOSFET are
its threshold voltage, the maximum drain-source voltage
BVDSS, and the on-resistance RDS(ON).
The gate drive for the MOSFET is guaranteed to be between
5V and 7.5V. This allows the use of logic level threshold
Figure 4. Start-up Waveform for Back-to-Back MOSFET Application
VOLTAGE
(5V/DIV)
TIME (2.5ms/DIV)
4352 FO4
CPO
GATE
OUT
VIN
VCC
VIN = 5V
C2 = 0.1μF
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