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參數(shù)資料
| 型號： | LTC4310IDD-1#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 電源管理 |
| 英文描述： | POWER SUPPLY SUPPORT CKT, PDSO10 |
| 封裝： | 3 X 3 MM, LEAD FREE, PLASTIC, MO-229WEED-2, DFN-10 |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 231K |
| 代理商： | LTC4310IDD-1#TRPBF |
LTC4310-1/LTC4310-2
4
431012fa
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
tMAX(TX)
Maximum Time Between TXP, TXN
Transmit Events
l
0.85
1.15
1.45
ms
tMAX(RX)
Maximum Time Between RXP, RXN
Receive Events
l
3.4
4.6
5.8
ms
Transmit Outputs
VTX(OL)
TXP, TXN Single-Ended Output Low
ISINK = 100A, VCC = 3V
l
1.5
5
mV
VTX(OH)
TXP, TXN Single-Ended Output High
15kΩ to GND on TXP, TXN; VCC = 3V, 5.5V l
0.95
1.25
1.52
V
tR(TX)
TXP, TXN Output Rise Time
CTXP , CTXN = 20pF
l
1
3
ns
tF(TX)
TXP, TXN Output Fall Time
CTXP , CTXN = 20pF
l
1
3
ns
tPWMIN(TX)
TXP, TXN Minimum Transmission
Pulse Width
VCC = 3V, 5.5V
l
31.5
35
39
ns
Receive Inputs
VRX(TH)
RXP, RXN Differential High Level
Threshold
RXP, RXN Pins; VCC = 3V, 5.5V
l
0.3
0.5
0.875
V
tPWMIN(RX)
RXP, RXN Minimum Received Pulse
Width
VCC = 3V, 5.5V
l
30
ns
RRX(IN)
RXP, RXN Differential Input Resistance
l
13
16.5
20
kΩ
elecTrical characTerisTics The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 3.3V, unless otherwise noted.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2. Guaranteed by design, not tested in production.
Note 3. SDA, SCL high-to-low propagation delay is measured from the
beginning of a new received message telling the LTC4310 to drive its SDA,
SCL pins from high to low, to when the SDA, SCL lines have fallen below
0.5 VCC. It includes approximately 87ns required for an LTC4310 to
receive a message on the RXP and RXN pins, plus the time the LTC4310
requires to process the message and pass the low to the data and clock
buffers, plus the time required by the buffers to drive their bus pins below
0.5 VCC.
Note 4. All currents into pins are positive, all voltages are referenced to
GND unless otherwise specified.
Note 5. Internal control circuitry prevents the rise time accelerators from
activating until the rising edge rate control circuitry is off.
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