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參數(shù)資料
| 型號： | LTC4310CMS-2#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 電源管理 |
| 英文描述： | POWER SUPPLY SUPPORT CKT, PDSO10 |
| 封裝： | LEAD FREE, PLASTIC, MSOP-10 |
| 文件頁數(shù)： | 3/20頁 |
| 文件大小： | 231K |
| 代理商： | LTC4310CMS-2#TRPBF |
LTC4310-1/LTC4310-2
11
431012fa
applicaTions inForMaTion
Figure 4. SCL1 Rising Waveform of SCL1
for Application Circuit Shown in Figure 1
Figure 5. 100kHz SCL Waveforms for
Application Circuit Shown in Figure 1
Bus Rising Edge Waveform
When all external pull-downs on SCL1 (Figure 1) turn off,
the SCL1 rising waveform will resemble that shown in
Figure 4. The LTC4310-1 senses that SCL1 is rising and
transmits a message to the other LTC4310-1 to release
SCL2 high. During the transmission, the first LTC4310-1
also drives SCL1 to 0.35V, so that when the transmission
is complete, both buses will rise simultaneously from
0.35V at a rate of (0.35 VCC)/900ns. This functionality
minimizestheeffectiveskewbetweenthetwobuses.When
SCL1 reaches 0.35 VCC, the LTC4310-1 deactivates its
rise rate regulation circuitry. The bus then rises with a
time constant of (RBUS CBUS) until it reaches 0.45 VCC,
at which point the IBOOST rise time accelerator pull-up
current is activated.
Figure 5 shows SCL1 and SCL2 for an entire 100kHz
switching cycle. Because the LTC4310-1 regulates the bus
rise rate to (0.35 VCC)/900ns, the 5V bus signal rises
more quickly than the 3.3V bus signal. Both buses reach
(0.35 VCC) in approximately 900ns, so the effective skew
betweenthebusesisnearlyzero.TheLTC4310-2functions
the same as the LTC4310-1, except the controlled rise rate
is limited to (0.35 VCC)/300ns.
1V/DIV
200ns/DIV
BUS RC
431012 F04
SCL1 SET TO 0.35V
DURING TX
RISE TIME
ACCELERATOR
ACTIVE
0.35 VCC
900 ns
dV/dt =
1V/DIV
2s/DIV
SCL1
SCL2
431012 F05
Start-Up, Data and Clock Hot Swap Circuitry
The LTC4310 contains power-on reset (POR) circuitry that
sets the data and clock pins in a high impedance state and
deactivates the transmit circuitry until the EN voltage is
high, the device is not in thermal shutdown and the VCC
voltage is above 2.4V. After the LTC4310 exits the POR
state, it activates its transmit circuitry and communicates
its SDA, SCL logic states across the barrier to the other
LTC4310 via its TXP and TXN pins.
The receive circuitry remains deactivated for an additional
900s after the LTC4310 exits POR. The 900s filter time is
required for the LTC4310 to charge its RXP and RXN pins
totheirDCbiasvoltage,assuminga0.01Fcommon-mode
noise filtering capacitor at the center-tap of the secondary
side of the external transformer. When the filter time has
elapsed, the LTC4310 activates its receive circuitry and
decodes the messages it receives on its RXP and RXN
pins, registering the logic state of the remote I2C bus.
Whenboththelocalandremotetwo-wirebusesare“quiet”
(i.e., no data transactions are occurring on either bus), the
LTC4310 then drives its READY pin low to indicate that it
has linked the logic state of the local I2C bus with the logic
state of the remote I2C bus. This means that the LTC4310
will now drive its SDA and SCL pins to the logic state of the
remote I2C bus, as specified by the messages it receives
on RXP and RXN. The LTC4310 considers a two-wire bus
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