參數(shù)資料
型號(hào): LTC4270AIUKG#PBF
廠商: LINEAR TECHNOLOGY CORP
元件分類: 模擬信號(hào)調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, PQCC52
封裝: 8 X 7 MM, LEAD FREE, PLASTIC, QFN-52
文件頁數(shù): 30/32頁
文件大小: 344K
代理商: LTC4270AIUKG#PBF
LTC4270/LTC4271
7
42701fa
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I2C Timing
fSCLK
Clock Frequency
(Note 7)
l
1
MHz
t1
Bus Free Time
Figure 5 (Notes 7, 9)
l
480
ns
t2
Start Hold Time
Figure 5 (Notes 7, 9)
l
240
ns
t3
SCL Low Time
Figure 5 (Notes 7, 9)
l
480
ns
t4
SCL High Time
Figure 5 (Notes 7, 9)
l
240
ns
t5
SDAIN Data Hold Time
Figure 5 (Notes 7, 9)
l
60
ns
t5
Data Clock to SDAOUT Valid
Figure 5 (Notes 7, 9)
l
130
ns
t6
Data Set-Up Time
Figure 5 (Notes 7, 9)
l
80
ns
t7
Start Set-Up Time
Figure 5 (Notes 7, 9)
l
240
ns
t8
Stop Set-Up Time
Figure 5 (Notes 7, 9)
l
240
ns
tr
SCL, SDAIN Rise Time
Figure 5 (Notes 7, 9)
l
120
ns
tf
SCL, SDAIN Fall Time
Figure 5 (Notes 7, 9)
l
60
ns
Fault Present to INT Pin Low
(Notes 7, 9, 10)
l
150
ns
Stop Condition to INT Pin Low
(Notes 7, 9, 10)
l
1.5
μs
ARA to INT Pin High Time
(Notes 7, 9)
l
1.5
μs
SCL Fall to ACK Low
(Notes 7, 9)
l
130
ns
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V and VDD – DGND = 3.3V unless otherwise noted.
(Notes 3 & 4)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. With the exception of (VDD
DGND), exposure to any Absolute Maximum Rating condition for extended
periods may affect device reliability and lifetime.
Note 2: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 140C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 3: All currents into device pins are positive; all currents out of device
pins are negative.
Note 4: The LTC4270 operates with a negative supply voltage (with respect
to AGND). To avoid confusion, voltages in this data sheet are referred to in
terms of absolute magnitude.
Note 5: tDIS is the same as tMPDO defined by IEEE 802.3at
Note 6: The LTC4271 digital interface operates with respect to DGND. All
logic levels are measured with respect to DGND.
Note 7: Guaranteed by design, not subject to test.
Note 8: The IEEE 802.3af specification allows a PD to present its
Maintain Power Signature (MPS) on an intermittent basis without being
disconnected. In order to stay powered, the PD must present the MPS for
tMPS within any tMPDO time window.
Note 9: Values Measured at VILD and VIHD
Note 10: If a fault condition occurs during an I2C transaction, the INT pin
will not be pulled down until a stop condition is present on the I2C bus.
Note 11: Load characteristics of the LTC4270 during Mark: 7V < (AGND –
VOUTn) < 10V or IOUT < 50μA.
Note 12: See the LTC4271 Software Programming documentation for
information on serial bus usage and device configuration and status
registers.
Note 13: Do not source or sink current from CAP1 and CAP2.
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