參數(shù)資料
型號(hào): LTC4267CGN-1#TR
廠商: LINEAR TECHNOLOGY CORP
元件分類: 穩(wěn)壓器
英文描述: 1 A SWITCHING CONTROLLER, 240 kHz SWITCHING FREQ-MAX, PDSO16
封裝: 0.150 INCH, PLASTIC, SSOP-16
文件頁數(shù): 21/32頁
文件大?。?/td> 925K
代理商: LTC4267CGN-1#TR
LTC4267-1
28
42671f
For the LTC4267-1 switching regulator, the current loop
through C1, T1 primary, Q1, and RSENSE must be given
careful layout attention. (Refer to Figure 11.) Because of
the high switching current circulating in this loop, these
components should be placed in close proximity to each
other. In addition, wide copper traces or copper planes
should be used between these components. If vias are
necessary to complete the connectivity of this loop,
placing multiple vias lined perpendicular to the ow of
current is essential for minimizing parasitic resistance and
reducing current density. Since the switching frequency
and the power levels are substantial, shielding and high
frequency layout techniques should be employed. A low
current, low impedance alternate connection should be
employed between the PGND pins of the LTC4267-1 and
the PGND side of RSENSE, away from the high current loop.
This Kelvin sensing will ensure an accurate representation
of the sense voltage is measured by the LTC4267-1.
The placement of the feedback resistors R1 and R2 as
well as the compensation capacitor CC is very important
in the accuracy of the output voltage, the stability of the
main control loop, and the load transient response. In
an isolated design application, R1, R2, and CC should be
placed as close as possible to the error amplier’s input
with minimum trace lengths and minimum capacitance.
In a nonisolated application, R1, and R2 should be placed
APPLICATIO S I FOR ATIO
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as close as possible to the VFB pin of the LTC4267-1
and CC should be placed close to the ITH/RUN pin of the
LTC4267-1.
In essence, a tight overall layout of the high current loop
and careful attention to current density will ensure suc-
cessful operation of the LTC4267-1 in a PD.
The PD interface section of the LTC4267-1 is relatively im-
mune to layout problems. Excessive parasitic capacitance
on the RCLASS pin should be avoided. The SIGDISA pin is
adjacent to the VPORTP pin and any coupling, whether resis-
tive or capacitive may inadvertently disable the signature
resistance. To ensure consistent behavior, the SIGDISA
pin should be electrically connected and not left oating.
Voltages in a PD can be as large as –57V, so high voltage
layout techniques should be employed.
Electro Static Discharge and Surge Protection
The LTC4267-1 is specied to operate with an absolute
maximum voltage of –100V and is designed to tolerate
brief overvoltage events. However, the pins that interface
to the outside world (primarily VPORTN and VPORTP) can
routinely see peak voltages in excess of 10kV. To protect
the LTC4267-1, it is highly recommended that a transient
voltage suppressor be installed between the diode bridge
and the LTC4267-1 (D3 in Figure 2).
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