參數(shù)資料
型號: LTC4252-2CMS8#PBF
廠商: LINEAR TECHNOLOGY CORP
元件分類: 電源管理
英文描述: Negative Voltage Hot Swap Controllers; Package: MSOP; No of Pins: 8; Temperature Range: 0°C to +70°C
中文描述: 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8
封裝: LEAD FREE, PLASTIC, MSOP-8
文件頁數(shù): 24/36頁
文件大?。?/td> 336K
代理商: LTC4252-2CMS8#PBF
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
30
425212fc
APPLICATIONS INFORMATION
425212 F19
–48RTN
UV
OV
VEE
VIN
SENSE
SS
TIMER
GATE
PWRGD
DRAIN
LTC4252A-1
R1
392k
1%
R2
30.1k
1%
CT
0.68μF
CSS
68nF
CC
10nF
–48V
RS
0.02Ω
Q1
IRF530S
VOUT
RC
10Ω
R5
100k
R4
38.3k
D1
BZV85C43
RIN
3
× 1.8k
1/4W EACH
1
9
8
10
3
2
7
6
4
5
C1
10nF
CIN
1μF
CL
100μF
–48RTN
(SHORT PIN)
+
RD 1M
R6 27Ω
LOAD
EN
*
*FMMT493
**DIODES, INC
RECOMMENDED FOR HARSH ENVIRONMENTS
DIN
DDZ13B**
Figure 19. Power Limit Circuit Breaking Application
Circuit Breaker with Foldback Current Limit
Figure 20 shows the LTC4252A in a foldback current limit
application. When VOUT is shorted to the –48V RTN supply,
current flows through resistors R4 and R5. This results in
a voltage drop across R5 and a corresponding reduction
in voltage drop across the sense resistor, RS, as the ACL
amplifier servos the sense voltage between the SENSE
and VEE pins to about 60mV. The short-circuit current
through RS reduces as the VOUT voltage increases during
an output short-circuit condition. Without foldback current
limiting resistor R5, the current is limited to 3A during
analog current limit. With R5, the short-circuit current is
limited to 0.5A when VOUT is shorted to 71V.
Inrush Control Without a Sense Resistor
During Power-Up
Figure 21 shows the LTC4252A in an application where the
inrush current is controlled without a sense resistor during
power-up. This setup is suitable only for applications that
don’t require short-circut protection from the LTC4252A.
Resistor R4 and capacitor C2 act as a feedback network
to accurately control the inrush current. The C2 capacitor
can be calculated with the following equation:
C2=
IGATE CL
IINRUSH
(19)
where IGATE = 58μA and CL is the total load capacitance.
Capacitor C3 and resistor R4 prevent Q1 from momen-
tarily turning on when the power pins first make contact.
Without C3 and R4, capacitor C2 pulls the gate of Q1 up
to a voltage roughly equal to VEE C2/CGS(Q1) before the
LTC4252A powers up. By placing capacitor C3 in parallel
with the gate capacitance of Q1 and isolating them from
C2 using resistor R4, the problem is solved. The value of
C3 is given by:
C3=
VSUPPLY(MAX)
VGS(TH),Q1
C2+CGD(Q1)
()
(20)
C3 ≈ 35 C2 for VSUPPLY(MAX) = 71V
where VGS(TH),Q1 is the MOSFET’s minimum gate threshold
and VSUPPLY(MAX) is the maximum operating input voltage.
Diode-ORing
Figure 22 shows the LTC4252 used as diode-oring with Hot
Swap capability in a dual – 48V power supply application.
The conventional diode-OR method uses two high power
diodes and heat sinks to contain the large heat dissipation
of the diodes. With the LTC4252 controlling the external
FETs Q2 and Q3 in a diode-OR manner, the small turn-on
voltage across the fully enhanced Q2 and Q3 reduces the
power dissipation significantly.
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