參數(shù)資料
型號: LTC4251CS6
廠商: LINEAR TECHNOLOGY CORP
元件分類: 電源管理
英文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO6
封裝: 1 MM HEIGHT, PLASTIC, MO-193, TSOT-23, 6 PIN
文件頁數(shù): 18/20頁
文件大小: 235K
代理商: LTC4251CS6
LTC4251/LTC4251-1/
LTC4251-2
7
425112fa
If SENSE exceeds 50mV while GATE is high, a 230
A pull-
up current charges CT. If SENSE drops below 50mV before
TIMER reaches 4V, a 5.8
A pull-down current slowly
discharges CT. In the event that CT eventually integrates up
to the 4V VTMRH threshold, TIMER latches high with a
5.8
A pull-up source and GATE quickly pulls low. The
LTC4251/LTC4251-1/LTC4251-2 fault latches may be
cleared by either pulling TIMER low with an external
device, or by pulling UV/OV below VUVLO.
UV/OV (Pin 5): Undervoltage/Overvoltage Input. This dual
function pin detects undervoltage as well as overvoltage.
The high threshold at the UV comparator is set at VUVHI
with VUVHST hysteresis. The high threshold at the OV
comparator is set at VOVHI with VOVHST hysteresis. If
UV/OV < VUVLO or UV/OV > VOVHI, GATE pulls low. If
UV/OV > VUVHI and UV/OV < VOVLO, the LTC4251/
LTC4251-1/LTC4251-2 attempt to start-up. The internal
UVLO at VIN always overrides UV/OV. A low at UV resets
an internal fault latch. A high at OV pulls GATE low but does
not reset the fault latch. A 1nF to 10nF capacitor at UV/OV
eliminates transients and switching noise from affecting
the UV/OV thresholds and prevents glitches at the GATE
pin.
GATE (Pin 6): N-Channel MOSFET Gate Drive Output. This
pin is pulled high by a 58
A current source. GATE is pulled
low by invalid conditions at VIN (UVLO), UV/OV, or the fault
latch. GATE is actively servoed to control fault current as
measured at SENSE. A compensation capacitor at GATE
stabilizes this loop. A comparator monitors GATE to
ensure that it is low before allowing an initial timing cycle,
GATE ramp up after an overvoltage event, or restart after
a current limit fault.
SENSE (Pin 1): Circuit Breaker/Current Limit SENSE Pin.
Load current is monitored by sense resistor RS connected
between SENSE and VEE, and controlled in three steps. If
SENSE exceeds VCB (50mV), the circuit breaker compara-
tor activates a 230
A TIMER pin pull-up current. The
LTC4251/LTC4251-1/LTC4251-2 latch off when CTcharges
to 4V. If SENSE exceeds VACL (100mV), the analog current
limit amplifier pulls GATE down and regulates the MOSFET
current at VACL/RS. In the event of a catastrophic short-
circuit, SENSE may overshoot 100mV. If SENSE reaches
VFCL (200mV), the fast current limit comparator pulls
GATE low with a strong pull-down. To disable the circuit
breaker and current limit functions, connect SENSE to VEE.
Kelvin-sense connections between the sense resistor and
the VEE and SENSE pins are strongly recommended, see
Figure 6.
VEE (Pin 2): Negative Supply Voltage Input. Connect this
pin to the negative side of the power supply.
VIN (Pin 3): Positive Supply Input. Connect this pin to the
positive side of the supply through a dropping resistor. A
shunt regulator typically clamps VIN at 13V. An internal
undervoltage lockout (UVLO) circuit holds GATE low until
the VIN pin is greater than VLKO (9.2V), overriding UV/OV.
If UV is high, OV is low and VIN comes out of UVLO, TIMER
starts an initial timing cycle before initiating a GATE ramp
up. If VIN drops below approximately 8.2V, GATE pulls low
immediately.
TIMER (Pin 4): Timer Input. TIMER is used to generate a
delay at start up, and to delay shutdown in the event of an
output overload. TIMER starts an initial timing cycle when
the following conditions are met: UV is high, OV is low, VIN
clears UVLO, TIMER pin is low, GATE is lower than VGATEL
and VSENSE – VEE < VCB. A pull-up current of 5.8A then
charges CT, generating a time delay. If CT charges to
VTMRH (4V) the timing cycle terminates, TIMER quickly
pulls low and GATE is activated.
UV/OV refers to the UV pin for the LTC4251-2. The OV comparator in the LTC4251-2 is disabled. All
references in the text to overvoltage, OV, VOVHI and VOVLO do not apply to the LTC4251-2.
PI FU CTIO S
UU
U
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