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參數(shù)資料
| 型號： | LTC4222IUH#PBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC32 |
| 封裝： | 5 X 5 MM, LEAD FREE, PLASTIC, MO-220WHHD-X, QFN-32 |
| 文件頁數(shù)： | 15/32頁 |
| 文件大?。?/td> | 280K |
| 代理商： | LTC4222IUH#PBF |
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LTC4222
22
4222fa
APPLICATIONS INFORMATION
S
ADDRESS
a7:a0
4222 F07
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
A: ACKNOWLEDGE (LOW)
A: NOT ACKNOWLEDGE (HIGH)
R: READ BIT (HIGH)
W: WRITE BIT (LOW)
S: START CONDITION
P: STOP CONDITION
COMMAND
DATA
b7:b0
0
W
00
0
b7:b0
A
AP
S
ADDRESS
a7:a0
COMMAND
DATA
b7:b0
0
W
00
0
4222 F08
X X X X X X X X
b7:b0
A
AP
S
ADDRESS
a7:a0
1 0
COMMAND
S
ADDRESS
R A
b7:b0 1
DATA
b7:b0
0
W
00
4222 F09
A
A P
Figure 7. LTC4222 Serial Bus SDA Write Byte Protocol
Figure 8. LTC4222 Serial Bus SDA Write Word Protocol
Figure 9. LTC4222 Serial Bus SDA Read Byte Protocol
Figure 6. Data Transfer Over I2C or SMBus
SCL
SDA
START
CONDITION
STOP
CONDITION
ADDRESS
R/W
ACK
DATA
ACK
DATA
ACK
1 - 7
8
9
4222 F06
a6 - a0
b7 - b0
1 - 7
8
9
1 - 7
8
9
P
S
alert, it acknowledges this address by broadcasting its
address and releasing the ALERT pin.
Acknowledge
The acknowledge signal is used in handshaking between
transmitter and receiver to indicate that the last byte of
data was received. The transmitter always releases the
SDA line during the acknowledge clock pulse. When the
slave is the receiver, it pulls down the SDA line so that it
remains LOW during this pulse to acknowledge receipt
of the data. If the slave fails to acknowledge by leaving
SDA high, then the master may abort the transmission by
generating a STOP condition. When the master is receiving
data from the slave, the master pulls down the SDA line
during the clock pulse to indicate receipt of the data. After
the last byte has been received the master leaves the SDA
line HIGH (not acknowledge) and issues a stop condition
to terminate the transmission.
Write Protocol
The master begins communication with a START con-
dition followed by the seven bit slave address and the
R/W bit set to zero, as shown in Figure 7. The addressed
LTC4222 acknowledges this and then the master sends
a command byte which indicates which internal register
the master wishes to write. The LTC4222 acknowledges
this and then latches the lower three bits of the command
byte into its internal Register Address pointer. The master
then delivers the data byte and the LTC4222 acknowledges
once more and latches the data into its control register.
The transmission is ended when the master sends a STOP
condition. If the master continues sending a second data
byte, as in a Write Word command, the second data byte
is acknowledged by the LTC4222 but ignored, as shown
in Figure 8.
Read Protocol
The master begins a read operation with a START con-
dition followed by the seven bit slave address and the
R/W bit set to zero, as shown in Figure 9. The addressed
LTC4222 acknowledges this and then the master sends
a command byte which indicates which internal register
the master wishes to read. The LTC4222 acknowledges
this and then latches the lower three bits of the command
byte into its internal Register Address pointer. The master
then sends a repeated START condition followed by the
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