參數(shù)資料
型號: LTC4215IUFD#PBF
廠商: Linear Technology
文件頁數(shù): 12/28頁
文件大?。?/td> 265K
描述: IC CNTRLR HOT SWAP 24-QFN
標(biāo)準(zhǔn)包裝: 73
類型: 熱交換控制器
應(yīng)用: 通用
內(nèi)部開關(guān):
電源電壓: 2.9 V ~ 15 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 24-QFN(5x4)
包裝: 管件
LTC4215/LTC4215-2
12
4215fe
 APPLICATIONS INFORMATION
A typical LTC4215 application is in a high availability system
in which a positive voltage supply is distributed to power
individual cards. The device measures card voltages and
currents and records past and present fault conditions.
The system queries each LTC4215 over the I
2
C periodically
and reads status and measurement information.
A basic LTC4215 application circuit is shown in Figure 1.
The following sections cover turn-on, turn-off and various
faults that the LTC4215 detects and acts upon. External
component selection is discussed in detail in the Design
Example section.
Turn-On Sequence
The power supply on a board is controlled by using an
external N-channel pass transistor (Q1) placed in the power
path. Note that resistor R
S
 provides current detection. Re-
sistors R1, R2 and R3 de ne undervoltage and overvoltage
levels. R5 prevents high frequency oscillations in Q1 and
R6 and C1 form an optional network that may be used to
provide an output dV/dt limited start-up.
Several conditions must be present before the external
MOSFET turns on. First the external supply, V
DD
, must
exceed its 2.84V undervoltage lockout level. Next the
internally generated supply, INTV
CC
, must cross its 2.64V
undervoltage threshold. This generates a 60約 to 120約
power-on-reset pulse. During reset the fault registers are
cleared and the control registers are set or cleared as
described in the register section.
After a power-on-reset pulse, the LTC4215 goes through
the following turn-on sequence. First the UV and OV pins
indicate that input power is within the acceptable range,
which is indicated by bits C0-C1 in Table 4. Second, the EN
pin is externally pulled low. Finally, all of these conditions
must be satis ed for the duration of 100ms to ensure that
any contact bounce during insertion has ended.
When these initial conditions are satis ed, the ON pin is
checked and its state written to bit A3 in Table 2. If it is
high, the external MOSFET is turned on. If the ON pin is
low, the external MOSFET is turned on when the ON pin is
brought high or if a serial bus turn-on command is sent
by setting bit A3.
The MOSFET is turned on by charging up the GATE with
a 20糀 current source. When the GATE voltage reaches
the MOSFET threshold voltage, the MOSFET begins to
turn on and the SOURCE voltage then follows the GATE
voltage as it increases.
When the MOSFET is turning on, it ramps inrush current
up linearly at a dI/dt rate selected by capacitor C
SS
. Once
the inrush current reaches the limit set by the FB pin, the
Figure 1. Typical Application
+
R3
3.4K
1%
PLUG-IN
CARD
R2
1.18k
1%
R5
10?/DIV>
RS
0.005?/DIV>
Q1
FDC653N
R7
30.1k
1%
V
OUT
12V
R8
3.57k
1%
4215 F01
C
L
330糉
C
F
0.1糉
R1
34.8k
1%
BACKPLANE
C3
0.1糉
C
TIMER
0.68糉
GND
SCL
ALERT
SDA
12V
R4
100k
Z1
P6KE16A
R6
15k
C1
6.8nF
UV V
DD
SENSE
+
SENSE

LTC4215UFD
GATE
ADR1
ADR2
ADR0
TIMER  INTV
CC
GND
SOURCE
OV
ON
SDAI
SDA0
SCL
ALERT
FB
ADIN
GPIO
EN
SS
C
SS
7.5nF
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