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參數(shù)資料
| 型號： | LTC4215IUFD-3#TR |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC24 |
| 封裝： | 4 X 5 MM, PLASTIC, MO-220, QFN-24 |
| 文件頁數(shù)： | 15/28頁 |
| 文件大小： | 307K |
| 代理商： | LTC4215IUFD-3#TR |
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LTC4215-1/LTC4215-3
22
421513fc
master acknowledges the transmitted data byte, as in a
ReadWordcommand,Figure10,theLTC4215-1/LTC4215-3
repeat the requested register as the second data byte.
Alert Response Protocol
When any of the fault bits in FAULT register D are set, an
optional bus alert is generated if the appropriate bit in
the ALERT register B is also set. If an alert is enabled, the
corresponding fault causes the GPIO2 pin to pull low. After
the bus master controller broadcasts the Alert Response
Address, the LTC4215-1/LTC4215-3 respond with their
address on the SDA line and then release GPIO2 as shown
in Figure 11. The GPIO2 line is also released if the device
is addressed by the bus master. The GPIO2 signal is not
pulled low again until the FAULT register indicates a differ-
ent fault has occurred or the original fault is cleared and it
occurs again. Note that this means repeated or continuing
faults do not generate alerts until the associated FAULT
register bit has been cleared.
APPLICATIONS INFORMATION
Table 1. LTC4215-1/LTC4215-3 Device Addressing
DESCRIPTION*
DEVICE
ADDRESS
DEVICE ADDRESS
LTC4215-1/LTC4215-3
ADDRESS PINS
h
76543210
ADR1
ADR0
Mass Write
BE
10111110
X
Alert Response
19
00011001
X
8
90
1001000
X
NC
L
9
92
1001001
X
H
NC
10
94
1001010
X
NC
11
96
1001011
X
NC
H
12
98
1001100
X
L
13
9A
1001101
X
H
14
9C
1001110
X
L
NC
15
9E
1001111
X
L
H
25
B2
1011001
X
H
L
*Subset of LTC4215 addresses
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