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參數(shù)資料
| 型號(hào)： | LTC4215IUFD-3#PBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC24 |
| 封裝： | 4 X 5 MM, LEAD FREE, PLASTIC, MO-220, QFN-24 |
| 文件頁數(shù)： | 4/28頁 |
| 文件大?。?/td> | 307K |
| 代理商： | LTC4215IUFD-3#PBF |
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LTC4215-1/LTC4215-3
12
421513fc
A typical LTC4215-1/LTC4215-3 application is in a high
availability system in which a positive voltage supply is
distributed to power individual cards. The device measures
card voltages and currents and records past and present
fault conditions. The system queries each LTC4215-1/
LTC4215-3 over the I2C periodically and reads status and
measurement information.
A basic LTC4215-1/LTC4215-3 application circuit is shown
in Figure 1. The following sections cover turn-on, turn-off
and various faults that the LTC4215-1/LTC4215-3 detect
and act upon. External component selection is discussed
in detail in the Design Example section.
Turn-On Sequence
The power supply on a board is controlled by using an
external N-channel pass transistor (Q1) placed in the power
path. Note that resistor RS provides current detection. Re-
sistors R1, R2 and R3 dene undervoltage and overvoltage
levels. R5 prevents high frequency oscillations in Q1, and
R6 and C1 form an optional network that may be used to
provide an output dV/dt limited start-up.
Figure 1. Typical Application
Several conditions must be present before the external
MOSFET turns on. First the external supply, VDD, must
exceed its 2.84V undervoltage lockout levels. Next the
internally generated supply, INTVCC, must cross its 2.64V
undervoltage threshold. This generates a 60μs to 120μs
power-on-reset pulse. During reset the fault registers are
cleared and the control registers are set or cleared as
described in the register section.
After a power-on-reset pulse, the LTC4215-1/LTC4215-3 go
through the following turn-on sequence. First the UV and
OV comparators indicate that input power is within the ac-
ceptable range, which is indicated by bits C0-C1 in Table 4.
Second, the EN pin is externally pulled low. Finally, all
of these conditions must be satised for the duration of
100ms to ensure that any contact bounce during inser-
tion has ended.
When these initial conditions are satised, the ON pin is
checked and its state written to bit A3 in Table 2. If it is
high, the external MOSFET is turned on. If the ON pin is
low, the external MOSFET is turned on when the ON pin
is brought high or if a serial bus turn-on command is sent
by setting bit A3.
APPLICATIONS INFORMATION
+
UV VDD SENSE
+
SENSE–
LTC4215-1
GATE
ADR1
ADR0
TIMER
SS
INTVCC
GND
EN
SOURCE
OV
ON
SDAI
SDA0
SCL
FB
GPIO3
GPIO2
GPIO1
ADIN
R3
3.4K
1%
PLUG-IN
CARD
R2
1.18k
1%
R5
10Ω
RS
0.005Ω
Q1
FDC653N
R7
30.1k
1%
VOUT
12V
R8
3.57k
1%
24k
4215 F01
CL
330μF
CF
0.1μF
CONNECTOR
2
CONNECTOR
1
R1
34.8k
1%
BACKPLANE
CSS
7.5nF
C3
0.1μF
CTIMER
0.68μF
GND
SCL
SDA
12V
24k
RESET
3.3V
Z1
P6KE16A
R6
15k
C1
6.8nF
NC
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