參數(shù)資料
型號(hào)： LTC4215CUFD-3#TRPBF
廠商： LINEAR TECHNOLOGY CORP
元件分類： 電源管理
英文描述： 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC24
封裝： 4 X 5 MM, LEAD FREE, PLASTIC, MO-220, QFN-24
文件頁數(shù)： 27/28頁
文件大?。?/td> 307K
代理商： LTC4215CUFD-3#TRPBF
LTC4215-1/LTC4215-3
8
421513fc
ADIN: ADC Input. A voltage between 0V and 1.235V ap-
plied to this pin is measured by the onboard ADC. Tie to
ground if unused.
ADR0, ADR1: Serial Bus Address Inputs. Tying these pins
to ground, to the INTVCC pin or leaving open congures
one of 9 possible addresses. See Table 1 in Applications
Information.
EN: Enable Input. Ground this pin to indicate a board is
present and enable the N-channel MOSFET to turn on. When
this pin is high, the MOSFET is not allowed to turn on. An
internal 10μA current source pulls up this pin. Transitions
on this pin are recorded in the Fault register. A high-to-low
transition activates the logic to read the state of the ON
pin and clear Faults. See Applications Information.
Exposed Pad (Pin 25): Exposed Pad may be left open or
connected to device ground.
FB: Foldback Current Limit and Power Good Input. A
resistive divider from the output is tied to this pin. When
the voltage at this pin drops below 1.235V, power is not
considered good. The power bad condition may result
in the GPIO1 pin pulling low or going high impedance
depending on the conguration of control register bits A6
and A7. Also a power bad fault is logged in this condition if
the LTC4215-1/LTC4215-3 have nished the start-up cycle
and the GATE pin is high (See Applications Information).
The start-up current limit folds back from a 25mV sense
voltage to 10mV as the FB pin voltage drops from 1.3V
to 0V. Foldback is not active once the part leaves start-up
and the current limit is increased to 75mV.
GATE: Gate Drive for External N-channel MOSFET. An
internal 20μA current source charges the gate of the
MOSFET. No compensation capacitor is required on the
GATE pin, but a resistor and capacitor network from this
pin to ground may be used to set the turn-on output
voltage slew rate (See Applications Information). During
turn-off there is a 1mA pull-down current. During a short
circuit or undervoltage lockout (VDD or INTVCC), a 450mA
pull-down current source between GATE and SOURCE is
activated.
GND: Device Ground.
GPIO1: General Purpose Input/Output and Signals Power
Good/Bad. Open drain logic output that is pulled to ground
if bit B6 is reset. Status register bit C6 indicates if GPIO1
is high or low. High impedance output (high) by default.
GPIO1 may also be congured to indicate power-good
or power-bad as detected by the FB pin in status bit C3.
See applications information. Tie to ground if unused.
Congure according to Table 2 and 3.
GPIO2: General Purpose Input/Output and Fault Alert
Output. Open drain logic output that is pulled to ground
when bit D6 is set. Status register bit C5 indicates if GPIO2
is high or low. GPIO2 may be congured as an output that
is pulled to ground when a fault occurs to alert the host
controller. A fault alert is enabled by the ALERT register.
GPIO2 is congured as a general purpose output (high)
with all alerts disabled by default. See Applications In-
formation. Tie to ground if unused. Congure according
to Tables 3 and 5.
GPIO3: General Purpose Input/Output. Open drain logic
output that is pulled to ground when bit D7 is set. Status
register bit C2 indicates if GPIO3 is high or low. GPIO3
is congured as output low by default. See Applications
Information. Tie to ground if unused. Congure accord-
ing to Table 5.
INTVCC: Low Voltage Supply Decoupling Output. Connect
a 0.1μF capacitor from this pin to ground.
ON: On Control Input. A rising edge turns on the external
N-channel MOSFET and a falling edge turns it off. This
pin also congures the state of the FET On bit in the con-
trol register (and hence the external MOSFET) at power
up. For example, if the ON pin is tied high, then the FET
On bit (A3 in Table 2) goes high 100ms after power-up.
Likewise if the ON pin is tied low then the part remains
off after power-up until the FET On bit is set high using
the I2C bus. A high-to-low transition on this pin clears
the fault register.
PIN FUNCTIONS
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PDF描述
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