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參數(shù)資料
| 型號(hào)： | LTC4151HDD#PBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO10 |
| 封裝： | 3 X 3 MM, LEAD FREE, PLASTIC, MO-229WEED-2, DFN-10 |
| 文件頁數(shù)： | 3/18頁 |
| 文件大?。?/td> | 476K |
| 代理商： | LTC4151HDD#PBF |
LTC4151
11
4151fc
APPLICATIONS INFORMATION
Table 1. LTC4151 Device Addressing*
DESCRIPTION
HEX DEVICE
ADDRESS
BINARY DEVICE ADDRESS
LTC4151
ADDRESS PINS
h
a6
a5
a4
a3
a2
a1
a0
R/W
ADR1
ADR0
Mass Write
CC
1
0
1
0
X
0
CE
1
0
1
X
H
L
1
D0
1
0
1
0
X
NC
H
2
D2
1
0
1
0
1
X
H
3
D4
1
0
1
0
1
0
X
NC
4
D6
1
0
1
0
1
X
NC
L
5
D8
1
0
1
0
X
L
H
6
DA
1
0
1
0
1
X
H
NC
7
DC
1
0
1
0
X
L
NC
8
DE
1
0
1
X
L
*H = Tie High; L = Tie to GND; NC = Open; X = Don’t Care
I2C Device Addressing
Nine distinct I2C bus addresses are configurable using the
three-state pins ADR0 and ADR1, as shown in Table 1.
Address bits a6, a5 and a4 are configured to (110) and
the least significant bit is the R/W bit. In addition, the
LTC4151willrespondtoamasswriteaddress(1100110)b
for writing to all LTC4151s, regardless of their individual
address settings.
Acknowledge
The acknowledge signal is used for handshaking between
the transmitter and the receiver to indicate that the last
byte of data was received. The transmitter always releases
the SDA line during the acknowledge clock pulse. The
LTC4151 pulls the SDA line low on the 9th clock cycle to
acknowledge receipt of the data. If the slave fails to ac-
knowledge by leaving SDA high, then the master can abort
the transmission by generating a Stop condition. When
the master is receiving data from the slave, the master
must pull down the SDA line during the clock pulse to
indicate receipt of a data byte, and that another byte is to
be read. After the last byte has been received the master
will leave the SDA line high (not acknowledge) and issue
a Stop condition to terminate the transmission.
Write Protocol
The master begins a write operation with a Start condition
followed by the seven bit slave address and the R/W bit
set to zero. After the addressed LTC4151 acknowledges
the address byte, the master then sends a command
byte which indicates which internal register the master
wishes to write. The LTC4151 acknowledges this and
then latches the lower three bits of the command byte
into its internal register address pointer. The master then
delivers the data byte and the LTC4151 acknowledges
once more and latches the data into its internal register.
If the master continues sending a second byte or more
data bytes, as in a Write Word or Write Page command,
the second byte or more data bytes will be acknowledged
by the LTC4151, the internal register address pointer
will increment automatically, and each byte of data will
be latched into an internal register corresponding to the
address pointer. The write operation terminates and the
register address pointer resets to 00h when the master
sends a Stop condition.
Read Protocol
The master begins a read operation with a Start condition
followed by the seven bit slave address and the R/W bit
set to zero. After the addressed LTC4151 acknowledges
the address byte, the master then sends a command
byte that indicates which internal register the master
wishes to read. The LTC4151 acknowledges this and then
latches the lower three bits of the command byte into its
internal register address pointer. The master then sends
a repeated Start condition followed by the same seven bit
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