參數(shù)資料
型號: LTC4007EUFD-1#TRPBF
廠商: LINEAR TECHNOLOGY CORP
元件分類: 穩(wěn)壓器
英文描述: 4A, High Efficiency, Standalone Li-Ion Battery Charger; Package: QFN; No of Pins: 24; Temperature Range: -40°C to +125°C
中文描述: BATTERY CHARGE CONTROLLER, 345 kHz SWITCHING FREQ-MAX, PQCC24
封裝: 4 X 5 MM, LEAD FREE, PLASTIC, QFN-24
文件頁數(shù): 13/24頁
文件大?。?/td> 269K
代理商: LTC4007EUFD-1#TRPBF
20
LTC4007-1
40071f
APPLICATIO S I FOR ATIO
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Disabling the Thermistor Function
If the thermistor is not needed, connecting a resistor
between DCIN and NTC will disable it. The resistor should
be sized to provide at least 10
Awiththeminimumvoltage
applied to DCIN and 10V at NTC. Do not exceed 30
A.
Generally, a 301k resistor will work for DCIN less than 15V.
A 499k resistor is recommended for DCIN between 15V
and 24V.
Conditioning Depleted Batteries
Severely depleted batteries, with less than 3.25V/cell,
should be conditioned with a trickle charge to prevent
possible damage. This trickle charge is typically 10% of
the 1C rate of the battery. The LTC4007-1 can automati-
cally trickle charge depleted batteries using the circuit in
Figure 11. If the battery voltage is less than 3.25V/cell
(3.173V/cell if CHEM is low) then the LOBAT indicator will
be low and Q4 is off. This programs the charging current
with RPROG = R6 + R14. Charging current is approximately
300mA. When the cell voltage becomes greater than 3.25V
the LOBAT indicator goes high, Q4 shorts out R13, then
RPROG = R6. Charging current is then equal to 3A.
PCB Layout Considerations
For maximum efficiency, the switch node rise and fall
times should be minimized. To prevent magnetic and
electrical field radiation and high frequency resonant prob-
lems, proper layout of the components connected to the IC
is essential. (See Figure 12.) Here is a PCB layout priority
list for proper layout. Layout the PCB using this specific
order.
General Rules
1. Input capacitors need to be placed as close as possible
to switching FET’s supply and ground connections.
Shortest copper trace connections possible. These
parts must be on the same layer of copper. Vias must
not be used to make this connection.
2. The control IC needs to be close to the switching FET’s
gate terminals. Keep the gate drive signals short for a
clean FET drive. This includes IC supply pins that con-
nect to the switching FET source pins. The IC can be
placed on the opposite side of the PCB relative to above.
3. Place inductor input as close as possible to switching
FET’s output connection. Minimize the surface area of
this trace. Make the trace width the minimum amount
needed to support current—no copper fills or pours.
Avoid running the connection using multiple layers in
parallel. Minimize capacitance from this node to any
other trace or plane.
4. Place the output current sense resistor right next to
the inductor output but oriented such that the IC’s
current sense feedback traces going to resistor are not
long. The feedback traces need to be routed together
as a single pair on the same layer at any given time with
smallest trace spacing possible. Locate any filter
component on these traces next to the IC and not at the
sense resistor location.
5. Place output capacitors next to the sense resistor
output and ground.
6. Output capacitor ground connections need to feed
into same copper that connects to the input capacitor
ground before tying back into system ground.
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