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參數(shù)資料
| 型號： | LTC3900HS8#TR |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING REGULATOR, PDSO8 |
| 封裝： | PLASTIC, SOP-8 |
| 文件頁數(shù)： | 20/20頁 |
| 文件大?。?/td> | 277K |
| 代理商： | LTC3900HS8#TR |
LTC3900
9
3900fb
applicaTions inForMaTion
time. The current sinking capability of the circuit is around
1mA. The timeout function can be disabled by connecting
the timer pin to GND.
Current Sense
The differential input current sense comparator is used
for sensing the voltage across the drain-to-source termi-
nals of Q4 through the CS+ and CS– pins. If the inductor
current reverses into the Q4 causing CS+ to rise above
CS– by more than 10.5mV, the LTC3900 pulls CG low. This
comparator is used to prevent inductor reverse current
buildupduringpowerdownorBurstModeoperation,which
may cause damage to the MOSFET. The 10.5mV input
threshold has a positive temperature coefficient, which
closely matches the TC of the external MOSFET RDS(ON).
The current sense comparator is only active 250ns after
CG goes high; this is to avoid any ringing immediately
after Q4 is switched on.
Under light load conditions, if the inductor average cur-
rent is less than half of its peak-to-peak ripple current,
the inductor current will reverse into Q4 during a portion
of the switching cycle, forcing CS+ to rise above CS–.
The current sense comparator input threshold is set at
10.5mV to prevent tripping under light load conditions.
If the product of the inductor negative peak current and
MOSFET RDS(ON) is higher than 10.5mV, the LTC3900 will
operate in discontinuous current mode. Figure 6 shows
the LTC3900 operating in discontinuous current mode;
the CG output goes low before the next negative SYNC
pulse, as soon as the inductor current becomes negative.
Discontinuous current mode is sometimes undesirable.
To disable discontinuous current mode operation, add a
resistor divider, RCS1 and RCS2 at the CS+ pin to increase
the 10.5mV threshold so that the LTC3900 operates in
continuous mode at no load.
The LTC3900 CS+ pin has an internal current sinking
clamp circuit (ZCS in the Block Diagram) that clamps the
pin to 11V. The clamp circuit is to be used together with
the external series resistor, RCS1 to protect the CS+ pin
from high Q4 drain voltage in the power transfer cycle.
During the power transfer cycle, Q4 is off, the drain volt-
age of Q4 is determined by the primary input voltage and
the transformer turns ratio. This voltage can be high and
may damage the LTC3900 if CS+ is connected directly to
the drain of Q4. The current sinking capability of the clamp
circuit is 5mA minimum.
SYNC
FG
CG
TIMER RESET
(INTERNAL)
TIMER
TIMEOUT
THRESHOLD
3900 F05
TIMEOUT
MISSING/LOW
POSITIVE
SYNC PULSE
TIMER RESET AFTER
RECEIVING POSITIVE
SYNC PULSE
TIMER DO NOT RESET
AT SECOND NEGATIVE
SYNC PULSE
Figure 5. Timer Waveforms with Incorrect SYNC Pulses
SG
SYNC
FG
CG
3900 F06a
INDUCTOR
CURRENT
0A
CURRENT SENSE
COMPARATOR TRIP
Figure 6a. Discontinuous Current Mode Operation at No Load
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