參數(shù)資料
型號: LTC3880IUJ-1#TRPBF
廠商: LINEAR TECHNOLOGY CORP
元件分類: 穩(wěn)壓器
英文描述: 0.1 A DUAL SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PQCC40
封裝: 6 X 6 MM, LEAD FREE, PLASTIC, WJJD-2, QFN-40
文件頁數(shù): 18/112頁
文件大小: 2182K
代理商: LTC3880IUJ-1#TRPBF
LTC3880/LTC3880-1
13
3880fa
PIN FUNCTIONS
FREQ_CFG (Pin 17): Frequency or Phase Set/Select Pin.
Connect a ±1% resistor divider between the chip VDD25
FREQ_CFGandSGNDinordertoselectswitchingfrequency
or phase. If the pin is left open, the IC will use the value
programmed in the NVM. Minimize capacitance when the
pin is open to assure accurate detection of the pin state.
VOUT0_CFG/VOUT1_CFG (Pin 18/Pin 19): Output Voltage
Select Pin. Connect a ±1% resistor divider between the
chip VDD25VOUTn_CFGandSGNDinordertoselectoutput
voltage. This voltage can be adjusted with the VTRIMn_CFG
pins. If the pin is left open, the IC will use the value pro-
grammed in the NVM. Minimize capacitance when the
pin is open to assure accurate detection of the pin state.
VTRIM0_CFG/VTRIM1_CFG (Pin 20/Pin 21): Voltage Trim
Select Pin. Connect a ±1% resistor divider between the
chip VDD25 VTRIMn_CFG and SGND in order to adjust
the output voltage set point. The VTRIMn_CFG settings
in conjunction with the VOUTn_CFG setting adjusts the
voltage set point. If the pin is left open, the IC will either
not modify the VOUTn_CFG setting or use NVM. Minimize
capacitance when the pin is open to assure accurate de-
tection of the pin state.
VDD25 (Pin 22): Internally Generated 2.5V power Supply
Output Pin. Bypass this pin to SGND with a low ESR 1F
capacitor. Do not load this pin with external current except
for the ±1% resistor dividers required for the configura-
tion pins.
WP (Pin 23): Write Protect Pin Active High. An internal
10A current source pulls the pin to VDD33. If WP is high,
the PMBus writes are restricted.
SHARE_CLK (Pin 24): Share Clock, Bidirectional Open-
Drain Clock Sharing Pin. Nominally 100kHz. Used to
synchronize the timing between multiple LTC3880s. Tie all
SHARE_CLK pins together. All LTC3880s will synchronize
to the fastest clock. A pull-up resistor to 3.3V is required.
VDD33 (Pin 25): Internally Generated 3.3V Power Supply
Output Pin. Bypass this pin to SGND with a low ESR 1F
capacitor. Do not load this pin with external current except
for the pull-up resistors required for GPIOn, SCLK, SYNC
and possibly RUNn, SDA and SCL.
VSENSE1 (Pin 27): Channel 1 Voltage Sense Input. This
input voltage is referenced to the SGND pin.
INTVCC (Pin 33) LTC3880: Internal Regulator 5V Out-
put. The control circuits are powered from this voltage.
Decouple this pin to PGND with a minimum of 4.7F low
ESR tantalum or ceramic capacitor.
EXTVCC (Pin 33) LTC3880-1: External Regulator 5V
input. The control circuits are powered from this voltage.
Decouple this pin to PGND with a minimum of 4.7F low
ESR tantalum or ceramic capacitor.
PGND(Pin34):PowerGroundPin.Connectthispinclosely
to the sources of the bottom N-channel MOSFETs, the (–)
terminal of CVCC and the (–) terminal of CIN.
VIN (Pin 35): Main Input Supply. Decouple this pin to
PGND with a capacitor (0.1F to 1F). For applications
where the main input power is 5V, tie the VIN and INTVCC
pins together.
BG0/BG1 (Pin 36/Pin 32): Bottom Gate Driver Outputs.
These pins drive the gates of the bottom N-Channel
MOSFETs between PGND and INTVCC.
BOOST0/BOOST1(Pin37/Pin31):BoostedFloatingDriver
Supplies. The (+) terminal of the booststrap capacitors
connect to these pins. These pins swing from a diode
voltage drop below INTVCC up to VIN + INTVCC.
TG0/TG1 (Pin 38/Pin 30): Top Gate Driver Outputs. These
aretheoutputsoffloatingdriverswithavoltageswingequal
to INTVCC superimposed on the switch node voltages.
SW0/ SW1 (Pin 39/Pin 29): Switch Node Connections to
Inductors. Voltage swings at the pins are from a Schottky
diode (external) voltage drop below ground to VIN.
TSNS0/TSNS1 (Pin 40/Pin 28): Channel 0,1 External
Diode Temperature Sense. Connect to the anode of a diode
connected PNP transistor and star connect the cathode to
SGND in order to sense remote temperature. If external
temperature sense elements are not installed, short pin
to ground and set the UT_FAULT_LIMIT to –275°C and
the UT_FAULT_RESPONSE to ignore.
SGND (Exposed Pad Pin 41): Signal Ground. All small-
signal and compensation components should connect to
this ground, which in turn connects to PGND at one point.
相關(guān)PDF資料
PDF描述
LTC3880IUJ#PBF 0.1 A DUAL SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PQCC40
LTC3880EUJ-1#TRPBF 0.1 A DUAL SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PQCC40
LTC3880EUJ-1#PBF 0.1 A DUAL SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PQCC40
LTC3880IUJ-1#PBF 0.1 A DUAL SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PQCC40
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