參數(shù)資料
型號(hào)： LTC3851AIMSE#PBF
廠商： LINEAR TECHNOLOGY CORP
元件分類： 穩(wěn)壓器
英文描述： SWITCHING REGULATOR, PDSO16
封裝： LEAD FREE, PLASTIC, MSOP-16
文件頁(yè)數(shù)： 11/30頁(yè)
文件大小： 430K
代理商： LTC3851AIMSE#PBF
LTC3851A
19
3851afa
applicaTions inForMaTion
Fault Conditions: Current Limit and Current Foldback
The LTC3851A includes current foldback to help limit
load current when the output is shorted to ground. If the
output falls below 40% of its nominal output level, the
maximum sense voltage is progressively lowered from
its maximum programmed value to about 25% of the that
value. Foldback current limiting is disabled during soft-
start or tracking. Under short-circuit conditions with very
low duty cycles, the LTC3851A will begin cycle skipping
in order to limit the short-circuit current. In this situation
the bottom MOSFET will be dissipating most of the power
but less than in normal operation. The short-circuit ripple
current is determined by the minimum on-time tON(MIN)
of the LTC3851A (≈90ns), the input voltage and inductor
value:
VOUT = 0.8V 1+
RB
RA
The resulting short-circuit current is:
ISC =
1/4MaxVSENSE
RSENSE
– 1
2
ΔIL(SC)
Programming Switching Frequency
To set the switching frequency of the LTC3851A, connect
a resistor, RFREQ, between FREQ/PLLFLTR and GND. The
relationship between the oscillator frequency and RFREQ
is shown in Figure 7. A 0.1F bypass capacitor should be
connected in parallel with RFREQ.
Phase-Locked Loop and Frequency Synchronization
The LTC3851A has a phase-locked loop (PLL) comprised
of an internal voltage-controlled oscillator (VCO) and a
phase detector. This allows the turn-on of the top MOSFET
to be locked to the rising edge of an external clock signal
applied to the MODE/PLLIN pin. This phase detector is
an edge sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
The output of the phase detector is a pair of complemen-
tary current sources that charge or discharge the external
filter network connected to the FREQ/PLLFLTR pin. Note
that the LTC3851A can only be synchronized to an external
clock whose frequency is within range of the LTC3851A’s
internal VCO.This is guaranteed to be between 250kHz and
750kHz. A simplified block diagram is shown in Figure 8.
If the external clock frequency is greater than the internal
oscillator’s frequency, fOSC, then current is sunk con-
tinuously from the phase detector output, pulling down
the FREQ/PLLFLTR pin. When the external clock frequency
is less than fOSC, current is sourced continuously, pull-
ing up the FREQ/PLLFLTR pin. If the external and internal
frequencies are the same but exhibit a phase difference,
the current sources turn on for an amount of time corre-
spondingtothephasedifference.ThevoltageontheFREQ/
PLLFLTR pin is adjusted until the phase and frequency of
the internal and external oscillators are identical. At the
stable operating point, the phase detector output is high
impedance and the filter capacitor CLP holds the voltage.
Figure 7. Relationship Between Oscillator Frequency
and Resistor Connected Between FREQ/PLLFLTR and GND
DIGITAL
PHASE/
FREQUENCY
DETECTOR
VCO
2.7V
RLP
CLP
3851A F08
FREQ/PLLFLTR
EXTERNAL
OSCILLATOR
MODE/
PLLIN
Figure 8. Phase-Locked Loop Block Diagram
RFREQ (k)
20
250
OSCILLA
TOR
FREQUENCY
(kHz)
500
550
600
650
300
350
400
450
700
750
40
60
80
100 120 140 160
3851 F07
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