參數(shù)資料
型號: LTC3835IGN-1
廠商: LINEAR TECHNOLOGY CORP
元件分類: 穩(wěn)壓器
英文描述: 3 A SWITCHING CONTROLLER, 580 kHz SWITCHING FREQ-MAX, PDSO16
封裝: 0.150 INCH, PLASTIC, SSOP-16
文件頁數(shù): 15/28頁
文件大?。?/td> 303K
代理商: LTC3835IGN-1
LTC3835-1
22
38351fc
APPLICATIONS INFORMATION
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 8. The Figure 9 illustrates the
current waveforms present in the various branches of the
synchronous regulator operating in the continuous mode.
Check the following in your layout:
1. Is the top N-channel MOSFET M1 located within 1cm
of CIN?
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return
of CINTVCC must return to the combined COUT (–) ter-
minals. The path formed by the top N-channel MOSFET,
Schottky diode and the CIN capacitor should have short
leads and PC trace lengths. The output capacitor (–)
terminals should be connected as close as possible
to the (–) terminals of the input capacitor by placing
the capacitors next to each other and away from the
Schottky loop described above.
3. Does the LTC3835-1 VFB pin resistive divider connect to the
(+) terminals of COUT? The resistive divider must be con-
nected between the (+) terminal of COUT and signal ground.
The feedback resistor connections should not be along the
high current input feeds from the input capacitor(s).
4. Are the SENSEand SENSE+ leads routed together with
minimum PC trace spacing? The lter capacitor between
SENSE+ and SENSEshould be as close as possible
to the IC. Ensure accurate current sensing with Kelvin
connections at the SENSE resistor.
5. Is the INTVCC decoupling capacitor connected close to
the IC, between the INTVCC and the power ground pins?
This capacitor carries the MOSFET drivers current peaks.
An additional 1μF ceramic capacitor placed immediately
next to the INTVCC and PGND pins can help improve
noise performance substantially.
6. Keep the switching node (SW), top gate node (TG), and
boost node (BOOST) away from sensitive small-signal
nodes, especially from the opposites channel’s voltage
and current sensing feedback pins. All of these nodes
have very large and fast moving signals and therefore
should be kept on the “output side” of the LTC3835-1
and occupy minimum PC trace area.
7. Use a modied “star ground” technique: a low imped-
ance, large copper area central grounding point on
the same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTVCC
decoupling capacitor, the bottom of the voltage feedback
resistive divider and the SGND pin of the IC.
CB
DB
CINTVCC
+
CIN
D1
OPTIONAL
1μF
CERAMIC
M1
M2
+
CVIN
VIN
RIN
TRACK/SS
SENSE+
SENSE
VFB
PLLLPF
PLLIN/MODE
RUN
ITH
SGND
TG
SW
BOOST
VIN
BG
INTVCC
PGND
LTC3835EGN-1
L1
COUT
VOUT
GND
+
RSENSE
fIN
3835-1 F08
Figure 8. LTC3835-1 Recommended Printed Circuit Layout Diagram
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