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參數(shù)資料
| 型號： | LTC3560IS6#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 2.1 A SWITCHING REGULATOR, 2700 kHz SWITCHING FREQ-MAX, PDSO6 |
| 封裝： | 1 MM HEIGHT, LEAD FREE, PLASTIC, MO-193, TSOT-23, 6 PIN |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 256K |
| 代理商： | LTC3560IS6#TRPBF |
LTC3560
10
3560fb
APPLICATIONS INFORMATION
Efciency Considerations
The efciency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efciency and which change would produce
the most improvement. Efciency can be expressed as:
Efciency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of
the losses in LTC3560 circuits: VIN quiescent current and
I2R losses. The VIN quiescent current loss dominates
the efciency loss at very low load currents whereas the
I2R loss dominates the efciency loss at medium to high
load currents. In a typical efciency plot, the efciency
curve at very low load currents can be misleading since
the actual power lost is of no consequence as illustrated
in Figure 3.
1. The VIN quiescent current is due to two components:
the DC bias current as given in the electrical charac-
teristics and the internal main switch and synchronous
switch gate charge currents. The gate charge current
results from switching the gate capacitance of the
internal power MOSFET switches. Each time the gate
is switched from high to low to high again, a packet of
charge, dQ, moves from VIN to ground. The resulting
dQ/dt is the current out of VIN that is typically larger
than the DC bias current. In continuous mode, IGATECHG
= f(QT + QB) where QT and QB are the gate charges of
the internal top and bottom switches. Both the DC bias
and gate charge losses are proportional to VIN and thus
their effects will be more pronounced at higher supply
voltages.
2. I2R losses are calculated from the resistances of the
internal switches, RSW, and external inductor RL. In
continuous mode, the average output current owing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET RDS(ON) and the duty cycle
(DC) as follows:
RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)
The RDS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Charateristics
curves. Thus, to obtain I2R losses, simply add RSW to
RL and multiply the result by the square of the average
output current.
Other losses including CIN and COUT ESR dissipative losses
and inductor core losses generally account for less than
2% total additional loss.
Thermal Considerations
In most applications the LTC3560 does not dissipate
much heat due to its high efciency. But, in applica-
tions where the LTC3560 is running at high ambient
temperature with low supply voltage and high duty cycles,
such as in dropout, the heat dissipated may exceed the
maximum junction temperature of the part. If the junction
temperature reaches approximately 150°C, both power
Figure 2. Setting the LTC3560 Output Voltage
VFB
GND
LTC3560
0.6V ≤ VOUT ≤ 5.5V
R2
R1
3560 F02
Figure 3. Power Lost vs Load Current
LOAD CURRENT (mA)
0.1
0.0001
POWER
LOST
(W)
0.01
1
10
1
100
1000
3560 F03
0.001
0.1
VIN = 3.6V
VIN = 4.2V
VIN = 5.5V
VOUT = 2.5V
Burst Mode OPERATION
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