參數(shù)資料
型號(hào): LTC3538EDCB#PBF
廠商: LINEAR TECHNOLOGY CORP
元件分類: 穩(wěn)壓器
英文描述: 0.8 A SWITCHING REGULATOR, 1200 kHz SWITCHING FREQ-MAX, PDSO8
封裝: 2 X 3 MM, LEAD FREE, PLASTIC, DFN-8
文件頁(yè)數(shù): 4/16頁(yè)
文件大小: 206K
代理商: LTC3538EDCB#PBF
LTC3538
12
3538fb
Closing the Feedback Loop
The LTC3538 incorporates voltage mode PWM control.
The control to output gain varies with operation region
(buck, boost, buck-boost), but is usually no greater than
15. The output lter exhibits a double pole response, as
given by:
FILTER _POLE =
1
2 π L COUT
Hz
(in buck mode)
FILTER _POLE =
V
IN
2 VOUT π L COUT
Hz
(in boost mode)
where L is in Henries and COUT is in Farads.
The output lter zero is given by:
FILTER _ ZERO =
1
2 π RESR COUT
Hz
where RESR is the equivalent series resistance of the
output capacitor.
A troublesome feature in boost mode is the right-half plane
zero (RHP), given by:
RHPZ =
V
IN
2
2 π IOUT L VOUT
Hz
The loop gain is typically rolled off before the RHP zero
frequency.
A simple Type I compensation network can be incorporated
to stabilize the loop, but at a cost of reduced bandwidth and
slower transient response. To ensure proper phase margin
using Type I compensation, the loop must be crossed
over a decade before the LC double pole. Referring to
Figure 4, the unity-gain frequency of the error amplier
with the Type I compensation is given by:
UG =
1
2 π R1CP1
Hz
1V
FB
CP1
VC
R2
3538 F04
+
1
2
VOUT
R1
Figure 4. Error Amplier with Type I Compensation
VIA TO GND PLANE
8
VIN
7
SW1
6
SW2
5
VOUT
1
FB
2
VC
3
GND
4
BURST
VOUT
3538 F03
Figure 3. LTC3538 Recommended PCB Layout
OPERATION
相關(guān)PDF資料
PDF描述
LTC3538EDCB 0.8 A SWITCHING REGULATOR, 1200 kHz SWITCHING FREQ-MAX, PDSO8
LTC3538EDCB#TR 0.8 A SWITCHING REGULATOR, 1200 kHz SWITCHING FREQ-MAX, PDSO8
LTC3541EDD-2 1.25 A SWITCHING REGULATOR, 2700 kHz SWITCHING FREQ-MAX, PDSO10
LTC3541EDD-2#TR 1.25 A SWITCHING REGULATOR, 2700 kHz SWITCHING FREQ-MAX, PDSO10
LTC3541EDD-3 1.25 A SWITCHING REGULATOR, 2700 kHz SWITCHING FREQ-MAX, PDSO10
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