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參數(shù)資料
| 型號： | LTC3533EDE#TR |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 7 A SWITCHING REGULATOR, 2000 kHz SWITCHING FREQ-MAX, PDSO14 |
| 封裝： | 4 X 3 MM, 0.75 MM HEIGHT, PLASTIC, MO-229WGED-3, DFN-14 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 313K |
| 代理商： | LTC3533EDE#TR |
LTC3533
6
3533f
PIN FUNCTIONS
RT (Pin 1): Programs the Frequency of the Internal Oscil-
lator. Connect a resistor from RT to ground.
f(kHz) = 33,170/RT (kΩ)
BURST (Pin 2): Used to set the Automatic Burst Mode
Threshold. Connect a resistor and capacitor in parallel
from this pin to ground. See the Applications Information
section for component value selection. For manual control,
ground the pin to force Burst Mode operation, connect to
VIN to force xed frequency PWM mode.
SGND (Pin 3): Signal ground for the IC.
SW1 (Pin 4): Switch Pin where Internal Switches A and B
are Connected. Connect inductor from SW1 to SW2. An
optional Schottky diode can be connected from SW1 to
ground for a moderate efciency improvement. Minimize
trace length to reduce EMI.
PGND1, PGND2 (Pins 5, 6): Power Ground for the Internal
NMOS Power Switches.
SW2 (Pin 7): Switch Pin where Internal Switches C and
D are Connected. An optional Schottky diode can be
connected from SW2 to VOUT for a moderate efciency
improvement. For applications with output voltages over
4.3V, this Schottky diode is required to ensure the SW2
pin does not exhibit excess voltage. Minimize trace length
to reduce EMI.
VOUT (Pin 8): Voltage Sensing Pin for PVOUT and Input
Supply Pin for Internal Circuitry Powered by PVOUT. A lter
capacitor is placed from VOUT to GND. A ceramic bypass
capacitor is recommended as close to the VOUT and GND
pins as possible.
PVOUT (Pin 9): Output of the Synchronous Rectier. A
lter capacitor is placed from PVOUT to PGND. A ceramic
bypass capacitor is recommended as close to the PVOUT
and PGND pins as possible.
VIN (Pin 10): Input Supply Pin. Internal VCC for the IC.
PVIN (Pin 11): Power VIN Supply Pin. A 10F ceramic
capacitor is recommended as close to the PVIN and PGND
pins as possible.
RUN/SS (Pin 12): Combined Enable and Soft-Start. Applied
voltage <0.4V shuts down the IC. Tie to >1.4V to enable
the IC and >1.6V to ensure the error amp is not clamped
from soft-start. An RC from the shutdown command signal
to this pin will provide a soft-start function by limiting the
rise time of VC
FB (Pin 13): Feedback Pin. Connect resistor divider tap
here. The output voltage can be adjusted from 1.8V to
5.25V. The feedback reference voltage is typically 1.22V.
V
RR
R
OUT =
+
122
12
2
.
VC (Pin 14): Error Amp Output. An R-C network is con-
nected from this pin to FB for loop compensation. Refer
to “Closing the Feedback Loop” section for component
selection guidelines. During Burst Mode operation, VC is
internally connected to a hold circuit.
Exposed Pad (Pin 15): IC Substrate Ground. This pin must
be soldered to the PCB ground to provide both electrical
contact and a good thermal contact to the PCB.
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| LTC3533EDE | 7 A SWITCHING REGULATOR, 2000 kHz SWITCHING FREQ-MAX, PDSO14 |
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