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參數(shù)資料
型號(hào): LTC2499CUHF#TRPBF
廠商: Linear Technology
文件頁數(shù): 14/34頁
文件大?。?/td> 0K
描述: IC ADC 24BIT DELTA SIG 38-QFN
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 24
采樣率(每秒): 7.5
數(shù)據(jù)接口: I²C,串行
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 480µW
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 38-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 38-QFN(5x7)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 16 個(gè)單端,雙極;8 個(gè)差分,雙極
配用: DC1012A-A-ND - BOARD DELTA SIGMA ADC LTC2499
LTC2499
2499fd
This value of slope can be used to calculate further tem-
perature readings using:
TK =
DATAOUT24
SLOPE
All Kelvin temperature readings can be converted to TC
(°C) using the fundamental equation:
TC = TK – 273
Initiating a New Conversion
When the LTC2499 finishes a conversion, it automatically
enters the sleep state. Once in the sleep state, the device is
ready for a read operation. After the device acknowledges
a read request, the device exits the sleep state and enters
the data output state. The data output state concludes
and the LTC2499 starts a new conversion once a STOP
condition is issued by the master or all 32 bits of data are
read out of the device.
Duringthedatareadcycle,aSTOPcommandmaybeissued
by the master controller in order to start a new conversion
and abort the data transfer. This STOP command must be
issued during the ninth clock cycle of a byte read when
the bus is free (the ACK/NACK cycle).
LTC2499 Address
The LTC2499 has three address pins (CA0, CA1, CA2).
Each may be tied HIGH, LOW, or left floating enabling one
of 27 possible addresses (see Table 5).
In addition to the configurable addresses listed in Table 5,
the LTC2499 also contains a global address (1110111)
whichmaybeusedforsynchronizingmultipleLTC2499sor
otherLTC24XXdelta-sigmaI2Cdevices(seeSynchronizing
Multiple LTC2499s with a Global Address Call section).
Operation Sequence
The LTC2499 acts as a transmitter or receiver, as shown
in Figure 6. The device may be programmed to perform
several functions. These include input channel selection,
measure the internal temperature, selecting the line fre-
quency rejection (50Hz, 60Hz, or simultaneous 50Hz and
60Hz), and a 2x speed mode.
Table 5. Address Assignment
CA2
CA1
CA0
ADDRESS
LOW
0010100
LOW
HIGH
0010110
LOW
Float
0010101
LOW
HIGH
LOW
0100110
LOW
HIGH
0110100
LOW
HIGH
Float
0100111
LOW
Float
LOW
0010111
LOW
Float
HIGH
0100101
LOW
Float
0100100
HIGH
LOW
1010110
HIGH
LOW
HIGH
1100100
HIGH
LOW
Float
1010111
HIGH
LOW
1110100
HIGH
1110110
HIGH
Float
1110101
HIGH
Float
LOW
1100101
HIGH
Float
HIGH
1100111
HIGH
Float
1100110
Float
LOW
0110101
Float
LOW
HIGH
0110111
Float
LOW
Float
0110110
Float
HIGH
LOW
1000111
Float
HIGH
1010101
Float
HIGH
Float
1010100
Float
LOW
1000100
Float
HIGH
1000110
Float
1000101
Continuous Read
Inapplicationswheretheinputchannel/configurationdoes
not need to change for each cycle, the conversion can be
continuously performed and read without a write cycle
(see Figure 7). The configuration/input channel remains
unchanged from the last value written into the device. If
the device has not been written to since power-up, the
configuration is set to the default value. At the end of a
read operation, a new conversion automatically begins.
At the conclusion of the conversion cycle, the next result
may be read using the method described above. If the
conversion cycle is not concluded and a valid address
applications inForMation
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