V
參數(shù)資料
型號(hào)： LTC2492CDE#PBF
廠商： Linear Technology
文件頁數(shù)： 15/36頁
文件大?。?/td> 0K
描述： IC ADC 24BIT DELTA SIG 14-DFN
標(biāo)準(zhǔn)包裝： 91
位數(shù)： 24
采樣率（每秒）： 7.5
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 800µW
電壓電源： 單電源
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 14-WFDFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 14-DFN-EP（4x3）
包裝： 管件
輸入數(shù)目和類型： 4 個(gè)單端，雙極；2 個(gè)差分，雙極
產(chǎn)品目錄頁面： 1348 (CN2011-ZH PDF)
配用： DC1009A-A-ND - BOARD DELTA SIGMA ADC LTC2492
LTC2492
22
2492fd
Hi-Z
2492 F07
CS
SCK
(EXTERNAL)
SDI
SDO
CONVERSION
SLEEP
DATA INPUT/OUTPUT
SLEEP
CONVERSION
VCC
fO
SCK
SDI
GND
6
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG
INPUTS
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
LTC2492
4-WIRE
SPI INTERFACE
EOC
BIT 28 BIT 27 BIT 26 BIT 25 BIT 24
BIT 23
BIT 29
BIT 30
BIT 31
12
3
4
5
6
7
8
1
0
EN
SGL
A2
A1
A0
ODD
DON'T CARE
MSB
SIG
“0”
REF+
REF–
CH0
CH1
CH2
CH3
COM
CS
SDO
12
1
13
14
8
9
10
11
7
3
4
5
2
2.7V TO 5.5V
0.1μF
10μF
APPLICATIONS INFORMATION
Typically, CS remains LOW during the data output/input
state. However, the data output state may be aborted by
pulling CS HIGH any time between the 1st falling edge
and the 32nd falling edge of SCK (see Figure 7). On the
rising edge of CS, the device aborts the data output state
and immediately initiates a new conversion. In order to
program a new input channel, 8 SCK clock pulses are
required. If the data output sequence is aborted prior to
the 8th falling edge of SCK, the new input data is ignored
and the previously selected input channel remains valid.
If the rising edge of CS occurs after the 8th falling edge of
SCK, the new input channel is loaded and valid for the next
conversion cycle. If CS goes high between the 8th falling
edge and the 16th falling edge of SCK, the new channel
is still loaded, but the converter conguration remains
unchanged. In order to program both the input channel
and converter conguration, CS must go high after the
16th falling edge of SCK (at this point all data has been
shifted into the device).
External Serial Clock, 3-Wire I/O
This timing mode uses a 3-wire serial I/O interface. The
conversion result is shifted out of the device by an externally
generated serial clock (SCK) signal (see Figure 8). CS is
permanently tied to ground, simplifying the user interface
or isolation barrier.
The external serial clock mode is selected at the end of
the power-on reset (POR) cycle. The POR cycle typically
concludes 4ms after VCC exceeds 2V. The level applied to
SCK at this time determines if SCK is internally generated
or externally applied. In order to enter the external SCK
mode, SCK must be driven LOW prior to the end of the
POR cycle.
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. EOC may be used as an interrupt to an
external controller. EOC = 1 while the conversion is in
progress and EOC = 0 once the conversion is complete.
Figure 7. External Serial Clock, Reduced Output Data Length and Valid Channel Selection
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