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參數(shù)資料
| 型號(hào)： | LTC2481 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | Easy-to-Use, Ultra-Tiny 16-Bit ADC |
| 中文描述： | 易于使用，超微型16位ADC |
| 文件頁數(shù)： | 9/20頁 |
| 文件大?。?/td> | 212K |
| 代理商： | LTC2481 |
LTC2450-1
9
24501fb
Conversion Status Monitor
For certain applications, the user may wish to monitor
the LTC2450-1 conversion status. This can be achieved
by holding SCK HIGH during the conversion cycle. In
this condition, whenever the
CS
input pin is pulled low
(
CS
= LOW), the SDO output pin will provide an indication
of the conversion status. SDO = HIGH is an indication of
a conversion cycle in progress while SDO = LOW is an
indication of a completed conversion cycle. An example
of such a sequence is shown in Figure 4.
Conversion status monitoring, while possible, s not required
for LTC2450-1 as its conversion time is fixed and equal at
approximately 16.6ms (21ms maximum). Therefore, ex-
ternal timing can be used to determine the completion of a
conversion cycle.
SERIAL INTERFACE
The LTC2450-1 transmits the conversion result and receives
the start of conversion command through a synchronous
3-wire interface. This interface can be used during the
CONVERT and SLEEP states to assess the conversion
status and during the DATA OUTPUT state to read the
conversion result, and to trigger a new conversion.
APPLICATIONS INFORMATION
Serial Interface Operation Modes
The following are a few of the more common interface
operation examples. Many more valid control and serial
data output operation sequences can be constructed based
upon the above description of the function of the three
digital interface pins.
The modes of operation can be summarized as follows:
1) The LTC2450-1 functions with SCK idle high (commonly
known as CPOL = 1) or idle low (commonly known as
CPOL = 0).
2) After the 16th bit is read, the user can choose one of
two ways to begin a new conversion. First, one can
pull
CS
high (
CS
=
↑
). Second, one can use a high-low
transition on SCK (SCK =
↓
)
.
3) At any time during the Data Output state, pulling
CS
high (
CS
=
↑
) causes the part to leave the I/O state,
abort the output and begin a new conversion.
4) When SCK = HIGH, it is possible to monitor the conver-
sion status by pulling
CS
low and watching for SDO
to go low. This feature is available only in the idle-high
(CPOL = 1) mode.
Figure 4. Conversion Status Monitoring Mode
SLEEP
t
1
t
2
SDO
SCK = HI
CONVERT
24501 F04
CS
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