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參數(shù)資料
| 型號： | LTC2453CTS8#TRMPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 4/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT DELTA SIG TSOT23-8 |
| 產品培訓模塊： | LTC2460 and LTC2450 Delta Sigma ADC Families |
| 標準包裝： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 60 |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉換器數(shù)目： | 2 |
| 功率耗散（最大）： | 4mW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-8 薄型，TSOT-23-8 |
| 供應商設備封裝： | TSOT-23-8 |
| 包裝： | 標準包裝 |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
| 產品目錄頁面： | 1348 (CN2011-ZH PDF) |
| 其它名稱： | LTC2453CTS8#TRMPBFDKR |
LTC2453
12
2453fc
ADC input pins. This capacitor is placed in parallel with
the ADC input parasitic capacitance CPAR. Depending
on the PCB layout, CPAR has typical values between 2pF
and 15pF. In addition, the equivalent circuit of Figure 9
includes the converter equivalent internal resistor RSW
and sampling capacitor CEQ.
Therearesomeimmediatetrade-offsinRSandCINwithout
needing a full circuit analysis. Increasing RS and CIN can
give the following benefits:
1) Due to the LTC2453’s input sampling algorithm, the
input current drawn by either VIN+ or VIN– over a con-
version cycle is 50nA. A high RS CIN attenuates the
high frequency components of the input current, and
RS values up to 1k result in <1LSB error.
2) The bandwidth from VSIG is reduced at the input pins
(IN+, IN–). This bandwidth reduction isolates the ADC
from high frequency signals, and as such provides
simple antialiasing and input noise reduction.
3) Switching transients generated by the ADC are attenu-
ated before they go back to the signal source.
4) A large CIN gives a better AC ground at the input pins,
helping reduce reflections back to the signal source.
5) Increasing RS protects the ADC by limiting the current
during an outside-the-rails fault condition.
There is a limit to how large RS CIN should be for a given
application. Increasing RS beyond a given point increases
Figure 10. Measured INL vs Input Voltage,
CIN = 0.1F, VCC = 5V, TA = 25°C
the voltage drop across RS due to the input current,
to the point that significant measurement errors exist.
Additionally, for some applications, increasing the RSCIN
product too much may unacceptably attenuate the signal
at frequencies of interest.
For most applications, it is desirable to implement CIN as
a high-quality 0.1F ceramic capacitor and RS ≤ 1k. This
capacitor should be located as close as possible to the
actualVINpackagepin.Furthermore,theareaencompassed
by this circuit path, as well as the path length, should be
minimized.
In the case of a 2-wire sensor that is not remotely
grounded, it is desirable to split RS and place series
resistors in the ADC input line as well as in the sensor
ground return line, which should be tied to the ADC GND
pin using a star connection topology.
Figure 10 shows the measured LTC2453 INL vs Input
Voltage as a function of RS value with an input capacitor
CIN = 0.1F.
Insomecases,RScanbeincreasedabovetheseguidelines.
The input current is zero when the ADC is either in sleep
or I/O modes. Thus, if the time constant of the input RC
circuit
t = RS CIN, is of the same order of magnitude or
longer than the time periods between actual conversions,
then one can consider the input current to be reduced
correspondingly.
Figure 11. Measured INL vs Input Voltage,
CIN = 0, VCC = 5V, TA = 25°C
APPLICATIONS INFORMATION
DIFFERENTIAL INPUT VOLTAGE (V)
–5
INL
(LSB)
2
6
10
3
2453 F10
–2
–6
0
4
8
–4
–8
–10
–3
–4
–1
–2
1
2
4
0
5
RS = 10k
RS = 2k
RS = 1k
RS = 0
CIN = 0.1F
VCC = 5V
TA = 25°C
DIFFERENTIAL INPUT VOLTAGE (V)
–5
INL
(LSB)
2
6
10
3
2453 F11
–2
–6
0
4
8
–4
–8
–10
–3
–4
–1
–2
1
2
4
0
5
RS = 10k
RS = 1k, 2k
RS = 0
CIN = 0
VCC = 5V
TA = 25°C
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